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US4906868A
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Logic circuit using bipolar complementary metal oxide semiconductor gate and semiconductor memory device having the logic circuit
Assignee: Fujitsu VLSI Ltd
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Filing: 1988-11-10
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Granted: 1990-03-06
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Expires: 2008-11-10
Abstract
Abstract A logic circuit improves a marginal voltage of a p-channel metal oxide semiconductor (MOS) transistor which is driven through a bipolar complementary metal oxide semiconductor (CMOS) gate. The logic circuit has a bipolar CMOS gate having a CMOS gate and output stage bipolar transistors for receiving an input signal through the CMOS gate, where the CMOS gate and the output stage bipolar transistors are driven by first and second power source voltages. The first power source voltage is higher than the second power source voltage and the output stage bipolar transistors output a signal as an output signal of the bipolar CMOS gate. A p-channel MOS transistor has a gate supplied with the output signal of the bipolar CMOS gate, a source supplied with a third power source voltage, and a drain from which an output signal of the logic circuit is outputted. The third power source voltage is a predetermined value lower than the first power source voltage and higher than the second power source voltage. As a result, the turning OFF of the p-channel MOS transistor is guaranteed due to the improved marginal voltage.
Inventors
- 👤 Yasuhiko Maki
- 👤 Osamu Nomura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:08
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/22; G11C7/00; G11C7/06; G11C7/062; G11C8/00; G11C8/08; H; H03; H03K; H03K19/00; H03K19/0021; H03K19/0027; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
193 words
A logic circuit for improving a marginal voltage of a p-channel metal oxide semiconductor (MOS) transistor which is driven through a bipolar complementary metal oxide semiconductor (CMOS) gate driven by first and second power source voltages, said logic circuit coupled to a third power source voltage and comprising: a bipolar CMOS gate including a CMOS gate and output stage bipolar transistors for receiving an input signal through said CMOS gate, said CMOS gate and said output stage bipolar transistors being driven by the first and second power source voltages, the first power source voltage being higher than the second power source voltage, said output stage transistors outputting a signal as an output signal of said bipolar CMOS gate; and a p-channel MOS transistor having a gate coupled to said output stage transistor, and supplied with the output signal of said bipolar CMOS gate, said p-channel MOS transistor having a source supplied with the third power source voltage, and a drain for providing an output signal of said logic circuit, the third power source voltage being a predetermined value lower than the first power source voltage and higher than the second power source voltage.
Claim 2
Dependent Claim
193 words
A logic circuit for improving a marginal voltage of a p-channel metal oxide semiconductor (MOS) transistor which is driven through a bipolar complementary metal oxide semiconductor (CMOS) gate driven by first and second power source voltages, said logic circuit coupled to a third power source voltage and comprising: a bipolar CMOS gate including a CMOS gate and output stage bipolar transistors for receiving an input signal through said CMOS gate, said CMOS gate and said output stage bipolar transistors being driven by the first and second power source voltages, the first power source voltage being higher than the second power source voltage, said output stage transistors outputting a signal as an output signal of said bipolar CMOS gate; and a p-channel MOS transistor having a gate coupled to said output stage transistor, and supplied with the output signal of said bipolar CMOS gate, said p-channel MOS transistor having a source supplied with the third power source voltage, and a drain for providing an output signal of said logic circuit, the third power source voltage being a predetermined value lower than the first power source voltage and higher than the second power source voltage.
Claim 3
Dependent Claim
80 words
A logic circuit as claimed in claim 1, wherein said output stage bipolar transistors are constituted by a pair of npn transistors coupled in series between the first and second power source voltages and output the output signal of said bipolar CMOS gate from a connection point between said pair of npn transistors, the first power source voltage being substantially 0 V, the second power source voltage being approximately -5.2 V, the third power source voltage being approximately -0.8 V.
Claim 4
Dependent Claim
173 words
A logic circuit coupled to first and second power source voltages, comprising: a bipolar CMOS gate, including: a CMOS gate for receiving an input signal; and output stage bipolar transistors, coupled to said CMOS gate, for receiving the input signal through said CMOS gate, said CMOS gate and said output stage bipolar transistors being driven by the first and second power source voltages, the first power source voltage being higher than the second power source voltage, said output stage bipolar transistors providing a first output signal; means for providing a third power source voltage of a predetermined value lower than the first power source voltage and higher than the second power source voltage; and a p-channel MOS transistor having a gate coupled to said output stage bipolar transistors, for receiving the first output signal provided by said output stage bipolar transistors, said p-channel MOS transistor having a source coupled to said means for providing the third power source voltage, and having a drain for providing a second output signal of said logic circuit.
Claim 5
Dependent Claim
173 words
A logic circuit coupled to first and second power source voltages, comprising: a bipolar CMOS gate, including: a CMOS gate for receiving an input signal; and output stage bipolar transistors, coupled to said CMOS gate, for receiving the input signal through said CMOS gate, said CMOS gate and said output stage bipolar transistors being driven by the first and second power source voltages, the first power source voltage being higher than the second power source voltage, said output stage bipolar transistors providing a first output signal; means for providing a third power source voltage of a predetermined value lower than the first power source voltage and higher than the second power source voltage; and a p-channel MOS transistor having a gate coupled to said output stage bipolar transistors, for receiving the first output signal provided by said output stage bipolar transistors, said p-channel MOS transistor having a source coupled to said means for providing the third power source voltage, and having a drain for providing a second output signal of said logic circuit.
Claim 6
Dependent Claim
49 words
A logic circuit as claimed in claim 3, wherein said output stage bipolar transistors are formed by a pair of npn transistors coupled in series between the first and second power source voltages, the first output signal being provided from a connection point between said pair of npn transistors.
Claim 7
Dependent Claim
37 words
A logic circuit as claimed in claim 4, wherein the first power source voltage is substantially 0 volts, the second power source voltage is substantially -5.2 volts, and the third power source voltage is substantially -0.8 volts.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-05 | 1993-09-04 | 1994-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-05 | 1997-09-04 | 1998-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-05 | 2001-09-04 | 2002-03-06 | $7700.00 | Window Closed / Lapsed |