Addressing multiple types of memory devices

Claim 2

A memory addressing system for a memory that has a plurality of banks of memory devices having a first and a second size, comprising: means for supplying address signals to said memory banks and for generating row and column accessing signals for said memory; a plurality of hardware configuration registers, each associated with at least one of said memory banks; means for programming said configuration registers to indicate the type of memory devioce that have been inserted in the particular memory banks and to indicate the starting address of the particular set of memory banks; and logic means, having inputs coupled to said means for supplying address signals and at least one of said configuration registers, for using the information in said configuration register to modify said accessing signals; whereby it is not necessary to insert the largest memory devices in the physical first memory banks and whereby memory devices of either size can be inserted in either set of memory banks.

Claim 3

The memory accessing system recited in claim 1 wherein said memory devices are in combination of 256K chips and 1 Meg chips.

Claim 4

The memory accessing system recited in claim 1 wherein said configuration registers store the size and starting address of the associated memory banks.

Claim 5

The memory accessing system recited in claim 1 including a nonvolatile memory for storing configuration data, and means for transferring data from said nonvolatile memory to said configuration registers when said memory accessing system is initialized.

Claim 6

A memory addressing system for a memory that has four banks of memory devices having a first and a second size, comprising: means for supplying address signals to said memory banks and for generating accessing signals for said memory, said memory banks being arranged in two pairs; two hardware configuration registers, one associated with each pair of memory banks; means for programming said configuration registers to indicate the size of the memory devices that have been inserted in the particular memory banks and to indicate the starting address of the particular set of memory banks; and logic means, having inputs coupled to said means for supplying address signals and at least one of said configuration registers, for modifying said access signals in accordance with the information in said configuration register to modify said accessing signals, whereby it is not necessary to insert the largest memory chips in the first memory bank and whereby memory chips of either size can be inserted in either set of memory banks.

Claim 7

A memory addressing system for a memory that has four banks of memory devices having a first and a second size, comprising: means for supplying address signals to said memory banks and for generating accessing signals for said memory, said memory banks being arranged in two pairs; two hardware configuration registers, one associated with each pair of memory banks; means for programming said configuration registers to indicate the size of the memory devices that have been inserted in the particular memory banks and to indicate the starting address of the particular set of memory banks; and logic means, having inputs coupled to said means for supplying address signals and at least one of said configuration registers, for modifying said access signals in accordance with the information in said configuration register to modify said accessing signals, whereby it is not necessary to insert the largest memory chips in the first memory bank and whereby memory chips of either size can be inserted in either set of memory banks.

Claim 8

The memory accessing system recited in claim 5 wherein said memory devices are a combination of 256K chips and 1 Meg chips.

Claim 9

The memory accessing recited in claim 5 wherein said configuration registers store the size and starting address of the associated memory bank.

Claim 10

A memory accessing system for a memory that has a plurality of physical banks of DRAMS having a first size and a second size with a nonvolatile memory associated with the accessing system for storing data indicating the size of the DRAMS and the starting address in each pair of memory banks, comprising: means for supplying address signals to said memory banks and for generating row and column accessing signals for said memory, said memory banks being arranged in pairs; a hardware configuration register associated with each pair of memory banks; means for transferring information from the nonvolatile memory to said configuration registers to indicate which of said sizes of DRAMS have been inserted in the particular memory banks and to indicate the starting address of the particular set of memory banks; and logic means, having inputs coupled to said means for supplying address signals and at least one of said configuration registers, for using the information in said configuration register to modify said row accessing signals, whereby it is not necessary to insert the largest memory chips in the first memory banks and whereby memory chips of either size can be inserted in either set of memory banks.

Claim 11

A memory accessing system for a memory that has a plurality of physical banks of DRAMS having a first size and a second size with a nonvolatile memory associated with the accessing system for storing data indicating the size of the DRAMS and the starting address in each pair of memory banks, comprising: means for supplying address signals to said memory banks and for generating row and column accessing signals for said memory, said memory banks being arranged in pairs; a hardware configuration register associated with each pair of memory banks; means for transferring information from the nonvolatile memory to said configuration registers to indicate which of said sizes of DRAMS have been inserted in the particular memory banks and to indicate the starting address of the particular set of memory banks; and logic means, having inputs coupled to said means for supplying address signals and at least one of said configuration registers, for using the information in said configuration register to modify said row accessing signals, whereby it is not necessary to insert the largest memory chips in the first memory banks and whereby memory chips of either size can be inserted in either set of memory banks.

Claim 12

A memory addressing system for a memory that has a first and a second bank of memory devices having a first and a second size, comprising: a first and a second configuration register, each register storing data representative of the first and second size and first an second starting address of the respective memory bank to which it is coupled; and a first and a second logic circuit, having inputs coupled to respective configuration registers, for generating a select signal in response to an address signal and to said start address data, said first logic circuit being coupled to the first memory bank and said second logic circuit being coupled to the second memory bank; such than an address signal input simultaneously to both logic circuits will cause a single select signal to select a memory bank as determined by said logic circuits in response to said data stored in said register irrespective of the relative sizes of the memory devices in each memory bank.

Claim 13

A memory addressing system for a memory that has a first and a second bank of memory devices having a first and a second size, comprising: a first and a second configuration register, each register storing data representative of the first and second size and first an second starting address of the respective memory bank to which it is coupled; and a first and a second logic circuit, having inputs coupled to respective configuration registers, for generating a select signal in response to an address signal and to said start address data, said first logic circuit being coupled to the first memory bank and said second logic circuit being coupled to the second memory bank; such than an address signal input simultaneously to both logic circuits will cause a single select signal to select a memory bank as determined by said logic circuits in response to said data stored in said register irrespective of the relative sizes of the memory devices in each memory bank.

Claim 14

The memory addressing system of claim 9, further comprising: means for programming said configuration registers to indicate the size of the memory devices that have been inserted in the particular memory bank and to indicate the starting address of the particular set of memory banks.

Claim 15

The memory addressing system of claim 9, further comprising: a non-volatile memory for storing configuration data; and means for transferring data from said non-volatile memory to said configuration registers when the memory accessing system is initialized.

Claim 16

A memory addressing system for a memory, comprising: a first memory bank, for storing a first particular number of bits, at a first physical location in the memory; a second memory bank, for storing a second particular number of bits, wherein the second particular number of bits is greater than said first particular number of bits, at a second physical location in said memory; a first and a second logic circuit, each logic circuit having a select output port, an address input port, a starting address input port and a size input port; said first logic circuit having its output coupled to said first memory bank and said second logic circuit having its output coupled to said second memory bank; a first and a second configuration register, each configuration register having an input port, a starting address output port, and a size output port, said first configuration register being coupled to said first logic circuit and said second configuration register being coupled to said second logic circuit at corresponding ports; said first configuration register storing size information corresponding to said first particular number of bits and having a start address corresponding to a number of words in said second memory bank; and said second configuration register storing size information corresponding to said second particular number of bits and storing a start address equal to a zero; such that in response to simultaneous address input to said first and second logic circuits, a selected signal will be output from a logic circuit corresponding to an address in said first and second memory banks for the location of data corresponding to said address input wherein respective starting addresses stored in said configuration registers indicate data is accessed on a bit boundary having an address evenly diversible by its size for logical placement of said first and second memory banks in said memory system without regard to the physical location of said memory banks in said memory system.

Claim 17

A memory addressing system for a memory, comprising: a first memory bank, for storing a first particular number of bits, at a first physical location in the memory; a second memory bank, for storing a second particular number of bits, wherein the second particular number of bits is greater than said first particular number of bits, at a second physical location in said memory; a first and a second logic circuit, each logic circuit having a select output port, an address input port, a starting address input port and a size input port; said first logic circuit having its output coupled to said first memory bank and said second logic circuit having its output coupled to said second memory bank; a first and a second configuration register, each configuration register having an input port, a starting address output port, and a size output port, said first configuration register being coupled to said first logic circuit and said second configuration register being coupled to said second logic circuit at corresponding ports; said first configuration register storing size information corresponding to said first particular number of bits and having a start address corresponding to a number of words in said second memory bank; and said second configuration register storing size information corresponding to said second particular number of bits and storing a start address equal to a zero; such that in response to simultaneous address input to said first and second logic circuits, a selected signal will be output from a logic circuit corresponding to an address in said first and second memory banks for the location of data corresponding to said address input wherein respective starting addresses stored in said configuration registers indicate data is accessed on a bit boundary having an address evenly diversible by its size for logical placement of said first and second memory banks in said memory system without regard to the physical location of said memory banks in said memory system.

Claim 18

A process for addressing a memory system, comprising the steps of: providing a first memory bank for storing a first particular number of bits stored in a first physical location of the memory system; providing a second memory bank for storing a second particular number of bits wherein said second number of bits is greater than said first particular number of bits, at a second physical location in the memory system; and rearranging addressing signals supplied to said memory system to provide that said second memory bank is assigned address locations corresponding to said first physical location wherein addressing of said first memory bank occurs logically after addresses of said second memory bank, which is arranged as a logical first memory bank.

Claim 19

A process for addressing a memory system, comprising the steps of: providing a first memory bank for storing a first particular number of bits stored in a first physical location of the memory system; providing a second memory bank for storing a second particular number of bits wherein said second number of bits is greater than said first particular number of bits, at a second physical location in the memory system; and rearranging addressing signals supplied to said memory system to provide that said second memory bank is assigned address locations corresponding to said first physical location wherein addressing of said first memory bank occurs logically after addresses of said second memory bank, which is arranged as a logical first memory bank.

Claim 20

A memory addressing system for a memory having a plurality of banks of memory devices, comprising: means for providing physical address signals to said banks of memory devices; means for receiving virtual memory address signals; logic means, coupled between said means for receiving and said means for providing, for programmably altering said virtual address signals to provide a different address as said physical address signal; means for programming said logic means in accordance with a size of said memory devices in each of said banks; and such that a bank having a smaller memory devices may have an earlier physical address than a second bank but a later virtual address than said second bank.

Claim 21

A memory addressing system for a memory having a plurality of banks of memory devices, comprising: means for providing physical address signals to said banks of memory devices; means for receiving virtual memory address signals; logic means, coupled between said means for receiving and said means for providing, for programmably altering said virtual address signals to provide a different address as said physical address signal; means for programming said logic means in accordance with a size of said memory devices in each of said banks; and such that a bank having a smaller memory devices may have an earlier physical address than a second bank but a later virtual address than said second bank.