Process for forming an integrated circuit on an N type substrate comprising PNP and NPN transistors placed vertically and insulated one from another

Claim 1

Process for forming an integrated circuit on a substrate of N type semiconductor material, comprising PNP and NPN transistors with vertical current flow, insulated from each other, in which: P + type regions are diffused on the N type substrate, said regions constituting the horizontal isolation region (2) of the NPN transistors and the low-resistivity collector region (3) of the PNP transistors, within the isolation region (2) a high-concentration N + type zone (4) is diffused, said zone acting as a low-resistivity collector region for the NPN transistor, an N type epitaxial layer (5) is then grown all over the surface of the device, P + type regions (6) and (7) are then diffused until they join with region (2), so as inside to define a region (10), and P + type regions (8) and (9) are diffused until they join with region (3), so as inside to define a region (11), regions (6), (2) and (7) all together acting as an isolation region for the NPN transistor, regions (3), (8) and (9) all together acting as a collector region for the PNP transistor, within the N type region (11), a P type region (12) is diffused to act as a low-concentration collector region for the PNP transistor, within the P type region (12), an N type region (13) is diffused to act as the base of the PNP transistor, within the N type regions (10) and (13), P type regions (14) and respectively (15) are diffused to act as the base of the NPN transistor and respectively as the emitter of the PNP transistor, within the P type region (14), an N type region (16) is diffused to act as the emitter of the NPN transistor, said diffusions of regions (2) and (4) being made to give the region (2) a surface concentration lower than that of the region (4), characterized in that said region 14 is realized in such a way to ensure that the low-concentration collector thickness (s1) of transistor NPN be practically equal to the low-concentration collector thickness (s2) of transistor PNP.