Semiconductor ic and method of making the same

Claim 2

A semiconductor IC comprising: a semiconductor substrate (31) of a first conductivity type (p), a semiconductor layer (33) formed on said substrate and of a second conductivity type (n) which is opposite to said first conductivity type, a first buried region (32) of said second conductivity type (n) buried between said semiconductor substrate (31) and said semiconductor layer (33), a second buried region (36) of said first conductivity type (p) buried on said first buried region (32), a collector region (39) of vertical transistor (39) of said first conductivity type of a low impurity concentration formed to extend from surface of said semiconductor layer (33) to said second buried region (36), a base region (41) of said vertical transistor of said second conductivity type (n) formed in said collector region (39) from surface thereof, and an emitter region (42) of said vertical transistor of said first conductivity type (p) formed in said base region from surface thereof; (e.g. Fig. 5).

Claim 3

A semiconductor IC comprising: a semiconductor substrate (31) of a first conductivity type (p), a first region (33) and a second region (33) formed isolated from each other on said substrate and of a second conductivity type (n) which is opposite to said first conductivity type, a fourth region (39) of a low impurity concentration of said first conductivity type (p) formed from surface of said first region (33), a fifth region (41) of said second conductivity type (n) formed from surface of said fourth region (39), a sixth region (42) of said first conductivity type (p) formed from surface of said fifth region, a seventh region (43) of said first conductivity type (p) formed from surface of said second region (33) at the same time as forming of said sixth region, an eighth region (45) of said second conductivity type (n) formed from surface of said fifth region (41), and a ninth region (46) of said second conductivity type (n) formed from surface of said seventh region (43), said eighth region (45) and said ninth region (46) being of simultaneous forming, and said fourth region (39), said fifth region (41) and said sixth region (42) forming a first vertical transistor of a first type (pnp) and said second region, said seventh region and said ninth region forming a second vertical transistor of a second type (npn); (e.g. Fig. 5).

Claim 4

A semiconductor IC comprising: a semiconductor substrate (31) of a first conductivity type (p), a first region (33) and a second region (33) formed isolated from each other on said substrate and of a second conductivity type (n) which is opposite to said first conductivity type, a fourth region (39) of a low impurity concentration of said first conductivity type (p) formed from surface of said first region (33), a fifth region (41) of said second conductivity type (n) formed from surface of said fourth region (39), a sixth region (42) of said first conductivity type (p) formed from surface of said fifth region, a seventh region (43) of said first conductivity type (p) formed from surface of said second region (33) at the same time as forming of said sixth region, an eighth region (45) of said second conductivity type (n) formed from surface of said fifth region (41), and a ninth region (46) of said second conductivity type (n) formed from surface of said seventh region (43), said eighth region (45) and said ninth region (46) being of simultaneous forming, and said fourth region (39), said fifth region (41) and said sixth region (42) forming a first vertical transistor of a first type (pnp) and said second region, said seventh region and said ninth region forming a second vertical transistor of a second type (npn); (e.g. Fig. 5).

Claim 5

A semiconductor IC in accordance with claim 2, which further comprises: a tenth region (32) of said second conductivity type buried between ' said semiconductor substrate (31) and said second region (33) and an eleventh region (38) of said second conductivity formed from surface of said first region (33) to reach said tenth region; (e.g. Fig. 5).

Claim 6

A semiconductor IC in accordance with claim 3, wherein said fifth region (41) and said eleventh region - (38) are connected each other; (e.g. Fig. 7).

Claim 7

A semiconductor IC in accordance with claim 2, which further comprises: a tenth region (32) of said second conductivity type buried between said semiconductor substrate (31) and said second region (33), and another buried region (36) of said first conductivity type formed on said tenth region (32) and contacting said fourth region (39); (e.g. Fig. 5).

Claim 8

A semiconductor IC comprising: a semiconductor substrate (31) of a first conductivity type (p), a first semiconductor region (33) a twelfth region (33) formed on said substrate and of a second conductivity type (n) which is opposite to said first conductivity type, a fourth region (39) of a low impurity concentration of said first conductivity type (p) formed from surface of said first semiconductor layer (33), a thirteenth region (48) and a fourteenth region (49) of said first conductivity type (p) formed from surface of said twelfth region (33) by simultaneous forming with said fourth region (39), a fifth region (41) of said second conductivity type (n) formed from surface of said fourth region (39), a sixth region (42), a fifteenth region (50) and a sixteenth region (51) of said first conductivity type (p) and of simultaneous forming from surfaces of said fifth region (41), said thirteenth region (48) and said fourteenth region (49), respectively, and an eighth region (45) and a seventeenth region (52) of said second conductivity type and of simultaneous forming from surfaces of said fifth region (41) and said fourteenth region (49), respectively, thereby a first vertical transistor (39+41+42) being formed in said first region (33 left) and an injection logic circuit (48+33+49+52) being formed in said twelfth region (33 right); (e.g. Fig. 8).

Claim 9

A semiconductor IC comprising: a semiconductor substrate (31) of a first conductivity type (p), a first semiconductor region (33) a twelfth region (33) formed on said substrate and of a second conductivity type (n) which is opposite to said first conductivity type, a fourth region (39) of a low impurity concentration of said first conductivity type (p) formed from surface of said first semiconductor layer (33), a thirteenth region (48) and a fourteenth region (49) of said first conductivity type (p) formed from surface of said twelfth region (33) by simultaneous forming with said fourth region (39), a fifth region (41) of said second conductivity type (n) formed from surface of said fourth region (39), a sixth region (42), a fifteenth region (50) and a sixteenth region (51) of said first conductivity type (p) and of simultaneous forming from surfaces of said fifth region (41), said thirteenth region (48) and said fourteenth region (49), respectively, and an eighth region (45) and a seventeenth region (52) of said second conductivity type and of simultaneous forming from surfaces of said fifth region (41) and said fourteenth region (49), respectively, thereby a first vertical transistor (39+41+42) being formed in said first region (33 left) and an injection logic circuit (48+33+49+52) being formed in said twelfth region (33 right); (e.g. Fig. 8).

Claim 10

A semiconductor IC in accordance with claim 6, wherein said fifteenth region (50) and said sixteenth region (51) are disposed in a manner to face each other with said twelfth region (33 right) inbetween; (e.g. Fig. 8).

Claim 11

A semiconductor IC in accordance with claim 6 or claim 7, wherein said fourteenth region (49) comprises an eighteenth region (53) of simultaneous forming with said fifth region (41) and of said second conductivity type, said eighteenth region (53) being disposed to include said seventeenth region (52) therein; (e.g. Fig. 9).

Claim 12

A semiconductor IC comprising: a semiconductor substrate (31) of a first conductivity type (p), a first region (33 left) and a nineteenth region (33 right) formed each other isolated on said substrate (31) and of a second conductivity type (n) which is opposite to said first conductivity type, a fourth region (39) of a low impurity concentration of said first conductivity type (p) formed from surface of said first region (33), a fifth region (41) of said second conductivity type (n) formed from surface of said fourth region (39), a twentieth region (102) of said second conductivity type (n) formed from surface of said nineteenth region (33 right), said fifth region (41) and said twentieth region (102) being of simultaneous forming, a sixth region (42) of said first conductivity type formed from surface of said fifth region (41), a twenty-first region (103) and a twenty-second region (104) of said first conductivity type (p) and formed from surface of said twentieth region (102), said sixth region (42), said twenty-first region (103) and said twenty-second region (104) being of simultaneous forming, an eighth region (45) of said second conductivity type (n) formed from surface of said fifth region (41), and a twenty-third region (105) of said second conductivity type (n) formed from surface of said twenty-second region (104), said fourth region (39), said fifth region (41) and said sixth region (42) forming a first vertical transistor of a first type (pnp) and said nineteenth region (33 right), said twentieth region (102), said twenty-first region (103), said twenty-second region (104) and said twenty-third region (105) forming a principal part of IIL; (e.g. Fig. 10).

Claim 13

A semiconductor IC comprising: a semiconductor substrate (31) of a first conductivity type (p), a first region (33 left) and a nineteenth region (33 right) formed each other isolated on said substrate (31) and of a second conductivity type (n) which is opposite to said first conductivity type, a fourth region (39) of a low impurity concentration of said first conductivity type (p) formed from surface of said first region (33), a fifth region (41) of said second conductivity type (n) formed from surface of said fourth region (39), a twentieth region (102) of said second conductivity type (n) formed from surface of said nineteenth region (33 right), said fifth region (41) and said twentieth region (102) being of simultaneous forming, a sixth region (42) of said first conductivity type formed from surface of said fifth region (41), a twenty-first region (103) and a twenty-second region (104) of said first conductivity type (p) and formed from surface of said twentieth region (102), said sixth region (42), said twenty-first region (103) and said twenty-second region (104) being of simultaneous forming, an eighth region (45) of said second conductivity type (n) formed from surface of said fifth region (41), and a twenty-third region (105) of said second conductivity type (n) formed from surface of said twenty-second region (104), said fourth region (39), said fifth region (41) and said sixth region (42) forming a first vertical transistor of a first type (pnp) and said nineteenth region (33 right), said twentieth region (102), said twenty-first region (103), said twenty-second region (104) and said twenty-third region (105) forming a principal part of IIL; (e.g. Fig. 10).

Claim 14

A semiconductor IC in accordance with claim 9, wherein said twenty-third region (116) is formed in said twentieth region (119); (e.g. Fig. 11).

Claim 15

A semiconductor IC comprising: a semiconductor substrate of a first conductivity type (p), a first region (33 left) and a nineteenth region (33 right) formed each other isolated on said substrate (31) and of a second conductivity type (n) which is opposite to said first conductivity type, a fourth region (39) of a low impurity concentration of said first conductivity type (p) formed from surface of said first region 133, a fifth region (41) of said second conductivity type (n) formed from surface of said fourth region (39), a twenty-fourth region (121) of low concentration and of said first conductivity type and of simultaneous forming with said fourth region, a twentieth region (122) of said second conductivity type formed from surface of said twenty-fourth region (121), said fifth region and said twentieth region being of simultaneous forming, a sixth region of said first conductivity type formed from surface of said fifth region (41), a twenty-first region (123) and a twenty-second region (51) of said first conductivity type formed from surface of the twentieth region (122) and twenty-fourth region (121) respectively, said sixth region (42), said twenty-first region (123) and said twenty-second region (52) being of simultaneous forming, an eighth region (45) of said second conductivity type (n) formed from surface of said fifth region (41), and a twenty-third region (52) of said second conductivity type formed from surface of said twenty fourth region (121), said fourth region (39), said fifth region (41) and said sixth region forming a first vertical transistor of a first type (pnp) and said nineteenth region (33 right), and said twentieth region (122), said twenty-first region (123), said twenty-second region (51), said twenty-third region (52) and said twenty-fourth region (121) forming a principal part of IIL; (e.g. Fig. 12).

Claim 16

A semiconductor IC comprising: a semiconductor substrate of a first conductivity type (p), a first region (33 left) and a nineteenth region (33 right) formed each other isolated on said substrate (31) and of a second conductivity type (n) which is opposite to said first conductivity type, a fourth region (39) of a low impurity concentration of said first conductivity type (p) formed from surface of said first region 133, a fifth region (41) of said second conductivity type (n) formed from surface of said fourth region (39), a twenty-fourth region (121) of low concentration and of said first conductivity type and of simultaneous forming with said fourth region, a twentieth region (122) of said second conductivity type formed from surface of said twenty-fourth region (121), said fifth region and said twentieth region being of simultaneous forming, a sixth region of said first conductivity type formed from surface of said fifth region (41), a twenty-first region (123) and a twenty-second region (51) of said first conductivity type formed from surface of the twentieth region (122) and twenty-fourth region (121) respectively, said sixth region (42), said twenty-first region (123) and said twenty-second region (52) being of simultaneous forming, an eighth region (45) of said second conductivity type (n) formed from surface of said fifth region (41), and a twenty-third region (52) of said second conductivity type formed from surface of said twenty fourth region (121), said fourth region (39), said fifth region (41) and said sixth region forming a first vertical transistor of a first type (pnp) and said nineteenth region (33 right), and said twentieth region (122), said twenty-first region (123), said twenty-second region (51), said twenty-third region (52) and said twenty-fourth region (121) forming a principal part of IIL; (e.g. Fig. 12).

Claim 17

A semiconductor IC comprising: a semiconductor substrate (31) of a first conductivity type (p), a first region (33 left) and a twenty-fifth region (33 right) formed isolated from each other on said substrate and of a second conductivity type (n) which is opposite to said first conductivity type, a fourth region (39) and a twenty-sixth region (131) both of a low impurity concentration of said first conductivity type (p) of simultaneous forming from surfaces of said first region (33 left) and said twenty-sixth region (131), respectively, a fifth region (41) and a twenty-seventh region (132) of said second conductivity type (n) formed from surfaces of said fourth region (39) and said twenty-sixth region (131), respectively, a sixth region (42) of said first conductivity type (p) formed from surfaces of said fifth region (41) and a twenty-ninth region (134) of said second conductivity type (n) formed from surface of said twenty-seventh region (132), said fourth region, said fifth region and said sixth region forming a first vertical transistor of a first type (pnp) and said twenty-fifth region, said twenty-sixth region, said twenty-seventh region and said twenty-ninth region forming a second vertical transistor of a second type (npn); (e.g. Fig. 13).

Claim 18

A semiconductor IC comprising: a semiconductor substrate (31) of a first conductivity type (p), a first region (33 left) and a twenty-fifth region (33 right) formed isolated from each other on said substrate and of a second conductivity type (n) which is opposite to said first conductivity type, a fourth region (39) and a twenty-sixth region (131) both of a low impurity concentration of said first conductivity type (p) of simultaneous forming from surfaces of said first region (33 left) and said twenty-sixth region (131), respectively, a fifth region (41) and a twenty-seventh region (132) of said second conductivity type (n) formed from surfaces of said fourth region (39) and said twenty-sixth region (131), respectively, a sixth region (42) of said first conductivity type (p) formed from surfaces of said fifth region (41) and a twenty-ninth region (134) of said second conductivity type (n) formed from surface of said twenty-seventh region (132), said fourth region, said fifth region and said sixth region forming a first vertical transistor of a first type (pnp) and said twenty-fifth region, said twenty-sixth region, said twenty-seventh region and said twenty-ninth region forming a second vertical transistor of a second type (npn); (e.g. Fig. 13).

Claim 19

A semiconductor IC comprising: a semiconductor substrate (31) of a first conductivity type (p), a first region (33 left) and a thirtieth region (33 right) formed isolated from each other on said substrate and of a second conductivity type (n) which is opposite to said first conductivity type, a fourth region (39) of a low impurity concentration of said first conductivity type (p) formed from surface of said first region (33), a fifth region (41) and a thirty-first region (141) of said second conductivity type (n) formed from surfaces of said fourth region (39) and said thirtieth region (33 right), respectively, a sixth region (42) and a thirty-second region (142) of said first conductivity type (p) formed from surface of said fifth region (41) and said thirtieth region (33), respectively, and an eighth region (45) and a thirty-third region (143) of said second conductivity type (n) formed from surfaces of said fifth region (41), and said thirty-second region (142), respectively, at the same time and said fourth region (39), said fifth region (41) and said sixth region (42) forming a first vertical transistor of a first type (pnp) and said thirtieth region (33 right), said thirty-first region (141), said thirty-second region (142) and said thirty-third region (143) forming a second vertical transistor of a second type (npn); (e.g. Fig. 14). 14. A semiconductor IC in accordance with claim 13, wherein said thirty-first region (141) is formed at the part. right under said thirty-third region (143); (e.g. Fig. 14).

Claim 20

A semiconductor IC comprising: a semiconductor substrate (31) of a first conductivity type (p), a first region (33 left) and a thirty-fourth region (33 right) formed each other isolated on said substrate and of a second conductivity type (n) which is opposite to said first conductivity type, a fourth region (39) and a thirty-fifth region (40) of a low impurity concentration of said first conductivity type (p) formed from surface of said first region (33 left) and said thirty-fourth region (33 right), respectively, a fifth region (41) of said second conductivity type (n) formed from surface ofsaid fourth region (39), a sixth region (42) and thirty-sixth regions (44) of said first conductivity type (p) formed from surface of said fifth region (41) and said thirty-fifth region (40), respectively, at the same time, and said fourth region, said fifth region and said sixth region forming a vertical transistor and said thirty-fifth region (40) and said thirty-sixth regions (44) forming a resistor; (e.g. Fig. 5).

Claim 21

A semiconductor IC comprising: a semiconductor substrate (31) of a first conductivity type (p), a first region (33 left) and a thirty-fourth region (33 right) formed each other isolated on said substrate and of a second conductivity type (n) which is opposite to said first conductivity type, a fourth region (39) and a thirty-fifth region (40) of a low impurity concentration of said first conductivity type (p) formed from surface of said first region (33 left) and said thirty-fourth region (33 right), respectively, a fifth region (41) of said second conductivity type (n) formed from surface ofsaid fourth region (39), a sixth region (42) and thirty-sixth regions (44) of said first conductivity type (p) formed from surface of said fifth region (41) and said thirty-fifth region (40), respectively, at the same time, and said fourth region, said fifth region and said sixth region forming a vertical transistor and said thirty-fifth region (40) and said thirty-sixth regions (44) forming a resistor; (e.g. Fig. 5).

Claim 22

A semiconductor IC comprising: a semiconductor substrate (31) of a first conductivity type (p), a first region (33 left) and a thirty-seventh region (33 right) formed each other isolated on said substrate and of a second conductivity type (n) which is opposite to said first conductivity type, a fourth region (39) and a thirty-eighth region (153) of a low impurity concentration of said first conductivity type (p) and of simultaneous forming formed from surfaces of said first region (33) and said thirty-seventh region (33 right), a fifth region (41) and a thirty-ninth region (151) of said second conductivity type (n) and of simultaneous forming formed from surface of said fourth region (39) and said thirty-eight region (153), a sixth region (42) of said first conductivity type (p) formed from surface of said fifth region, said fourth region (39), said fifth region (41) and said sixth region (42) forming a first vertical transistor of a first type (pnp) and said thirty-eighth region (153) and said thirty-ninth region (151) forming a resistor; (e.g. Fig. 15).

Claim 23

A semiconductor IC comprising: a semiconductor substrate (31) of a first conductivity type (p), a first region (33 left) and a thirty-seventh region (33 right) formed each other isolated on said substrate and of a second conductivity type (n) which is opposite to said first conductivity type, a fourth region (39) and a thirty-eighth region (153) of a low impurity concentration of said first conductivity type (p) and of simultaneous forming formed from surfaces of said first region (33) and said thirty-seventh region (33 right), a fifth region (41) and a thirty-ninth region (151) of said second conductivity type (n) and of simultaneous forming formed from surface of said fourth region (39) and said thirty-eight region (153), a sixth region (42) of said first conductivity type (p) formed from surface of said fifth region, said fourth region (39), said fifth region (41) and said sixth region (42) forming a first vertical transistor of a first type (pnp) and said thirty-eighth region (153) and said thirty-ninth region (151) forming a resistor; (e.g. Fig. 15).

Claim 24

A semiconductor IC in accordance with claim 16, which further comprises a tenth region (32 left) and a fourtieth region (32 right) of said second conductivity type formed as buried regions, at a first part which is between said substrate (31) and said first region (33 left), and at a second part which is between said substrate (31) and said thirty-seventh region (33 right), respectively, and a third region (36) and a fourty-first region (155) of said first conductivity type formed as overriding buried regions in said tenth region (33 left) and a fortieth region (32 right) in a manner to contact said fourth region (39) and said thirty-eighth region (153), respectively; (e.g. Fig. 15).

Claim 25

A semiconductor IC comprising: a semiconductor substrate (31) of a first conductivity type (p), a first region (33 left) and a forty-second region (33 right) formed each other isolated on said substrate and of a second conductivity type (n) which is opposite to said first conductivity type, a fourth region (39) and a forty-third region (161) of a low impurity concentration of said first conductivity type (p) and of simultaneous forming formed from surface of said first region (33) and said forty-second region (33 right), respectively, a fifth region (41) and a forty-fourth region (162) of said second conductivity type (n) and of simultaneous forming formed from surface of said fourth region (39) and said forty-third region (161), respectively, a sixth region (42) of said first conductivity type (p) formed from surface of said fifth region, an eighth region (45) and a forty-fifth region (163) of said second conductivity type (n) formed from surfaces of said fifth region (41) and said forty-fourth region (163), respectively, said fourth region (39), said fifth region (41) and said sixth region (42) forming a first vertical transistor, and said forty-third region, said forty-fourth region and said forth-fifth region forming a cross-over part; (e.g. Fig. 16).

Claim 26

A semiconductor IC comprising: a semiconductor substrate (31) of a first conductivity type (p), a first region (33 left) and a forty-second region (33 right) formed each other isolated on said substrate and of a second conductivity type (n) which is opposite to said first conductivity type, a fourth region (39) and a forty-third region (161) of a low impurity concentration of said first conductivity type (p) and of simultaneous forming formed from surface of said first region (33) and said forty-second region (33 right), respectively, a fifth region (41) and a forty-fourth region (162) of said second conductivity type (n) and of simultaneous forming formed from surface of said fourth region (39) and said forty-third region (161), respectively, a sixth region (42) of said first conductivity type (p) formed from surface of said fifth region, an eighth region (45) and a forty-fifth region (163) of said second conductivity type (n) formed from surfaces of said fifth region (41) and said forty-fourth region (163), respectively, said fourth region (39), said fifth region (41) and said sixth region (42) forming a first vertical transistor, and said forty-third region, said forty-fourth region and said forth-fifth region forming a cross-over part; (e.g. Fig. 16).

Claim 27

A semiconductor IC in accordance with claim 18, which further comprises a tenth region (32 left) and a forty-sixth region (32 right) of said second conductivity type formed as buried regions, at a first part which is between said substrate (31) and said first region (33 left), and at a second part which is between said substrate and said forty-second region (33 right), respectively, and a third region (36) and a forty-seventh region (169) of said first conductivity type formed as overriding buried regions in said tenth region (32) and said forty-sixth region in a manner to contact said fourth region (39) and said forty-second region (161), respectively; (e.g. Fig. 16).

Claim 28

Method of making a semiconductor IC comprising the steps of: introducing at parts (32) to form vertical npn transistor and vertical pnp transistor on a semiconductor substrate (31) of a first conductivity type (p), an impurity to make a second conductivity type (n) which is opposite to said first conductivity type, introducing at parts (34) to form isolation regions, at parts to form said vertical pnp transistor and at parts to form n-channel MOS transistor on said substrate, an impurity to make said first conductivity type (p), forming an epitaxial layer (33) on said substrate (31), introducing said first conductivity type impurity on the surface of said epitaxial layer (33) at parts (71) to form said isolation regions, at parts (39) to form said vertical pnp transistor and at the parts to form said n-channel MOS transistor (171 left), introducing said second conductivity (n) impurity on the surface of said epitaxial layer at the part to form a p-channel MOS transistor (171) and the part to form base region of said vertical pnp transistor (41), and introducing said first conductivity (p) impurity on the surface of said epitaxial layer at the parts to form source regions and drain regions of a first p-channel MOS transistor (177), a second p-channel MOS transistor (178), emitter region of said pnp transistor (42) and base region of said npn transistor (43); (e.g. 17C).

Claim 29

Method of making a semiconductor IC comprising the steps of: introducing at parts (32) to form vertical npn transistor and vertical pnp transistor on a semiconductor substrate (31) of a first conductivity type (p), an impurity to make a second conductivity type (n) which is opposite to said first conductivity type, introducing at parts (34) to form isolation regions, at parts to form said vertical pnp transistor and at parts to form n-channel MOS transistor on said substrate, an impurity to make said first conductivity type (p), forming an epitaxial layer (33) on said substrate (31), introducing said first conductivity type impurity on the surface of said epitaxial layer (33) at parts (71) to form said isolation regions, at parts (39) to form said vertical pnp transistor and at the parts to form said n-channel MOS transistor (171 left), introducing said second conductivity (n) impurity on the surface of said epitaxial layer at the part to form a p-channel MOS transistor (171) and the part to form base region of said vertical pnp transistor (41), and introducing said first conductivity (p) impurity on the surface of said epitaxial layer at the parts to form source regions and drain regions of a first p-channel MOS transistor (177), a second p-channel MOS transistor (178), emitter region of said pnp transistor (42) and base region of said npn transistor (43); (e.g. 17C).

Claim 30

Method in accordance with claim 20, wherein a second conductivity type impurity is introduced in a part to form IIL.

Claim 31

Method in accordance with claim 20, wherein a second conductivity type impurity is introduced in a part to form a high resistance device.

Claim 32

Method in accordance with claim 20, wherein a first conductivity type impurity is introduced in a part to form a high resistance device.