US4893316A
Expired / Lapsed
US
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Digital radio frequency receiver
Assignee: Motorola Solutions Inc
•
Filing: 1986-07-24
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Granted: 1990-01-09
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Expires: 2006-07-24
Abstract
Abstract A digital radio receiver is described. The digital receiver of the present invention contemplates a digital radio receiver which operates on a received analog signal which has been converted to a digital form after preselection at the output of the antenna. The digital receiver of the present invention comprises a preselector, a high-speed analog-to-digital (A/D) converter, a digitally implemented intermediate-frequency (IF) selectivity section having an output signal at substantially baseband frequencies, and digital signal processor (DSP) circuit performing demodulation and audio filtering. The radio architecture of the present invention is programmably adaptable to virtually every known modulation scheme and is particularly suitable for implementation on integrated circuits.
Inventors
- 👤 Robert V. Janc
- 👤 Steven C. Jasper
- 👤 Lester A. Longley
- 👤 Katherine L. Zebrose
- 👤 William J. Turney
- 👤 Ross J. Lillie
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 08:44
CPC Classifications
H; H03; H03D; H03D3/00; H03D3/007; H03C; H03C3/00; H03C3/38; H03C3/40; H03D1/00; H03D1/22; H03D1/2245; H03D7/00; H03D7/16; H03D7/165; H03D7/166; H03B; H03B27/00; H03B28/00; H03D2200/00; H03D2200/0041; H03D2200/005; H03D2200/0052; H03D3/006
Claims Analysis
Total Claims: 180
Claim 1
Independent Claim
205 words
An apparatus for extending the threshold sensitivity of an analog to digital (A/D) converter that converts an analog alternating current (AC) input signal having a given frequency into digital data, comprising: means for generating a noise signal which does not have any substantial energy at said given frequency; means for summing said analog AC input signal and said noise signal to produce a resultant signal that is coupled to an input of the A/D converter; clock means for generating periodic pulses at a first frequency coupled to said A/D converter causing the latter to make A/D conversions in response to said pulses; and the resultant signal produced by said summing means containing the signal component corresponding to said analog AC input signal which is converted by the A/D converter into a digital data representation, said A/D converter having a given threshold sensitivity and the magnitude of said AC input signal being less than said threshold sensitivity, said signal component corresponding to the AC input signal being converted by the A/D into digital data, whereby AC input signals having a magnitude less than said given threshold sensitivity of the A/D converter can be converted into digital data thereby extending the threshold sensitivity of the A/D converter.
Claim 2
Independent Claim
205 words
An apparatus for extending the threshold sensitivity of an analog to digital (A/D) converter that converts an analog alternating current (AC) input signal having a given frequency into digital data, comprising: means for generating a noise signal which does not have any substantial energy at said given frequency; means for summing said analog AC input signal and said noise signal to produce a resultant signal that is coupled to an input of the A/D converter; clock means for generating periodic pulses at a first frequency coupled to said A/D converter causing the latter to make A/D conversions in response to said pulses; and the resultant signal produced by said summing means containing the signal component corresponding to said analog AC input signal which is converted by the A/D converter into a digital data representation, said A/D converter having a given threshold sensitivity and the magnitude of said AC input signal being less than said threshold sensitivity, said signal component corresponding to the AC input signal being converted by the A/D into digital data, whereby AC input signals having a magnitude less than said given threshold sensitivity of the A/D converter can be converted into digital data thereby extending the threshold sensitivity of the A/D converter.
Claim 3
Dependent Claim
34 words
The apparatus according to claim 1 wherein said generating means generates a noise signal that produces quantization noise at the digital data output from the A/D converter having an essentially uniform power spectral density.
Claim 4
Dependent Claim
15 words
The apparatus according to claim 1 wherein said generating means generates a Gaussian noise signal.
Claim 5
Dependent Claim
27 words
The apparatus according to claim 1 wherein said generating means generates a noise signal having an amplitude less than the maximum voltage range of the A/D converter.
Claim 6
Dependent Claim
27 words
The apparatus according to claim 4 wherein the amplitude of the noise signal is approximately 15 decibels less than the maximum voltage range of the A/D converter.
Claim 7
Dependent Claim
32 words
The apparatus according to claim 1 further comprising a clock means for generating periodic pulses coupled to said A/D converter causing the latter to make A/D conversions in response to said pulses.
Claim 8
Dependent Claim
29 words
The apparatus according to claim 6 wherein the ratio of the rate of said periodic pulses to the bandwidth of said analog AC input signal is greater than 10.
Claim 9
Dependent Claim
39 words
The apparatus according to claim 6 further comprising means for periodically sampling the amplitude of the analog AC input signal and storing the sampled amplitude, said stored amplitude of the analog AC input signal coupled to said summing means.
Claim 10
Dependent Claim
36 words
The apparatus according to claim 8 wherein said sampling means includes means for generating sampling pulses having a time duration of less than 0.5 times the reciprocal of the frequency of said analog AC input signal.
Claim 11
Dependent Claim
29 words
The apparatus according to claim 1 wherein the first frequency of the pulses generated by said clock means is less than the given frequency of said AC input signal.
Claim 12
Independent Claim
175 words
A method for extending the threshold sensitivity of an analog to digital (A/D) converter that converts an analog alternating current (AC) input signal having a given frequency into digital data comprising the steps of: generating a noise signal which does not have any substantial energy at said given frequency; summing the analog AC input signal and said noise signal to produce a resultant signal which contains a signal component corresponding to said AC input signal; coupling the resultant signal to the input of the A/D converter; generating periodic clock pulses at a first frequency which are coupled to said A/D converter and cause A/D conversions to be made in response to said pulses; and the A/D converter converting said signal component into digital data representative of said analog AC input signal, said A/D converter having a given threshold sensitivity and the magnitude of said AC input signal being less than said threshold sensitivity, wherein converting by the A/D converter of the signal component into digital data effectively extends the threshold sensitivity of the A/D converter.
Claim 13
Independent Claim
175 words
A method for extending the threshold sensitivity of an analog to digital (A/D) converter that converts an analog alternating current (AC) input signal having a given frequency into digital data comprising the steps of: generating a noise signal which does not have any substantial energy at said given frequency; summing the analog AC input signal and said noise signal to produce a resultant signal which contains a signal component corresponding to said AC input signal; coupling the resultant signal to the input of the A/D converter; generating periodic clock pulses at a first frequency which are coupled to said A/D converter and cause A/D conversions to be made in response to said pulses; and the A/D converter converting said signal component into digital data representative of said analog AC input signal, said A/D converter having a given threshold sensitivity and the magnitude of said AC input signal being less than said threshold sensitivity, wherein converting by the A/D converter of the signal component into digital data effectively extends the threshold sensitivity of the A/D converter.
Claim 14
Dependent Claim
39 words
The method according to claim 11 further comprising the steps of periodically sampling the amplitude of the analog AC input signal, storing the sampled amplitude, and summing the stored amplitude with the noise signal to produce said resultant signal.
Claim 15
Dependent Claim
37 words
The method according to claim 12 wherein said sampling step includes the step of generating sampling pulses having a time duration of less than 0.5 times the reciprocal of the frequency of said analog AC input signal.
Claim 16
Dependent Claim
23 words
The method according to claim 11 further comprising the step of generating periodic clock pulses which cause corresponding A/D conversions to be made.
Claim 17
Dependent Claim
29 words
The method according to claim 12 wherein the ratio of the rate of the clock pulses to the bandwidth of the analog AC input signal is greater than 10.
Claim 18
Dependent Claim
24 words
The method according to claim 11 wherein the first frequency of said pulse is less than the given frequency of said AC input signal.
Claim 19
Dependent Claim
219 words
In a communications receiver having a bandpass filter with a bandwidth which permits the passage of an analog radio frequency (RF) input signal having a frequency within a predetermined range of frequencies and an analog to digital (A/D) converter having a digital data output, the improvement comprising: means for generating a noise signal which does not have any substantial energy within said range of frequencies; means for summing said filtered analog RF input signal and said noise signal to produce a resultant signal that is coupled to an input of the A/D converter; clock means for generating periodic pulses at a first frequency coupled to the A/D converter causing the latter to make A/D conversions in response thereto; said summing means producing a resultant signal containing a signal component corresponding to said analog RF input signal which is converted by the A/D converter into a digital data representation, said A/D converter having a given threshold sensitivity and the magnitude of said AC input signal being less than said threshold sensitivity, said signal component corresponding to the AC input signal being converted by the A/D into digital data, whereby AC input signals having a magnitude less than said given threshold sensitivity of the A/D converter can be converted into digital data thereby extending the threshold sensitivity of the A/D converter.
Claim 20
Dependent Claim
219 words
In a communications receiver having a bandpass filter with a bandwidth which permits the passage of an analog radio frequency (RF) input signal having a frequency within a predetermined range of frequencies and an analog to digital (A/D) converter having a digital data output, the improvement comprising: means for generating a noise signal which does not have any substantial energy within said range of frequencies; means for summing said filtered analog RF input signal and said noise signal to produce a resultant signal that is coupled to an input of the A/D converter; clock means for generating periodic pulses at a first frequency coupled to the A/D converter causing the latter to make A/D conversions in response thereto; said summing means producing a resultant signal containing a signal component corresponding to said analog RF input signal which is converted by the A/D converter into a digital data representation, said A/D converter having a given threshold sensitivity and the magnitude of said AC input signal being less than said threshold sensitivity, said signal component corresponding to the AC input signal being converted by the A/D into digital data, whereby AC input signals having a magnitude less than said given threshold sensitivity of the A/D converter can be converted into digital data thereby extending the threshold sensitivity of the A/D converter.
Claim 21
Dependent Claim
34 words
The apparatus according to claim 17 wherein said generating means generates a noise signal that produces quantization noise at the digital data output from the A/D converter having an essentially uniform power spectral density.
Claim 22
Dependent Claim
15 words
The apparatus according to claim 17 wherein said generating means generates a Gaussian noise signal.
Claim 23
Dependent Claim
27 words
The apparatus according to claim 17 wherein said generating means generates a noise signal having an amplitude less than the maximum voltage range of the A/D converter.
Claim 24
Dependent Claim
27 words
The apparatus according to claim 20 wherein the amplitude of the noise signal is approximately 15 decibels less than the maximum voltage range of the A/D converter.
Claim 25
Dependent Claim
29 words
The apparatus according to claim 17 further comprising clock means for generating periodic pulses coupled to the A/D converter causing the latter to make A/D conversions in response thereto.
Claim 26
Dependent Claim
29 words
The apparatus according to claim 22 wherein the ratio of the rate of said periodic pulses to the bandwidth of said analog A input signal is greater than 10.
Claim 27
Dependent Claim
45 words
The apparatus according to claim 22 further comprising means for periodically sampling the amplitude of the filtered analog RF input signal and storing the sampled amplitude, said stored amplitude coupled to said summing means and summed with said noise signal to produce said resultant signal.
Claim 28
Dependent Claim
36 words
The apparatus according to claim 24 wherein said sampling means includes means for generating sampling pulses having a time duration of less than 0.5 times the reciprocal of the frequency of said analog RF input signal.
Claim 29
Dependent Claim
24 words
The receiver according to claim 17 wherein the first frequency of said pulses is less than the given frequency of said AC input signal.
Claim 30
Independent Claim
152 words
A method for converting an analog radio frequency (RF) signal having a given frequency into digital data comprising the steps of: bandpass filtering said analog RF signal; storing a first signal corresponding to an instantaneous magnitude of said filtered analog RF signal; generating a noise signal which does not have any substantial energy at said given frequency; summing said first signal and said noise signal to produce a resultant signal; coupling said resultant signal to an analog to digital (A/D) converter; generating periodic clock pulses at a first frequency which are coupled to said A/D converter and cause A/D conversions to be made in response to said pulses, said A/D converter having a given threshold sensitivity and the magnitude of said RF signal being less than said threshold sensitivity, wherein the converting by the A/D converter of the signal component into digital data effectively extends the threshold sensitivity of the A/D converter.
Claim 31
Independent Claim
152 words
A method for converting an analog radio frequency (RF) signal having a given frequency into digital data comprising the steps of: bandpass filtering said analog RF signal; storing a first signal corresponding to an instantaneous magnitude of said filtered analog RF signal; generating a noise signal which does not have any substantial energy at said given frequency; summing said first signal and said noise signal to produce a resultant signal; coupling said resultant signal to an analog to digital (A/D) converter; generating periodic clock pulses at a first frequency which are coupled to said A/D converter and cause A/D conversions to be made in response to said pulses, said A/D converter having a given threshold sensitivity and the magnitude of said RF signal being less than said threshold sensitivity, wherein the converting by the A/D converter of the signal component into digital data effectively extends the threshold sensitivity of the A/D converter.
Claim 32
Dependent Claim
31 words
The method according to claim 27 further comprising the step of periodically sampling the instantaneous magnitude of said analog RF signal and storing a first signal corresponding to said sampled magnitude.
Claim 33
Dependent Claim
36 words
The method according to claim 28 wherein said sampling step includes the step of generating sampling pulses having a time duration of less than 0.5 times the reciprocal of the frequency of said analog RF signal.
Claim 34
Dependent Claim
22 words
The method according to claim 27 further comprising the step of generating periodic clock pulses causing corresponding A/D conversions to be made.
Claim 35
Dependent Claim
28 words
The method according to claim 30 wherein the ratio of the rate of the clock pulses to the bandwidth of the analog RF signal is greater than 10.
Claim 36
Dependent Claim
24 words
The method according to claim 27 wherein the first frequency of said pulses is less than the given frequency of said AC input signal.
Claim 37
Independent Claim
156 words
An apparatus for extending the threshold sensitivity of an analog to digital (A/D) converter that converts an analog alternating current (AC) input signal having a given frequency into digital data, comprising: means for generating a noise signal which does not have any substantial energy at said given frequency; means for summing said analog AC input signal and said noise signal to produce a resultant signal that is coupled to an input of the A/D converter; clock means for generating periodic pulses at a first frequency coupled to said AD converter causing the latter to make A/D conversions in response to said pulses, the ratio of the rate of said periodic pulses to the bandwidth of said analog AC input signal being greater than 10; and the resultant signal produced by said summing means containing a signal component corresponding to said analog AC input signal which is converted by the A/D converter into a digital data representation.
Claim 38
Independent Claim
156 words
An apparatus for extending the threshold sensitivity of an analog to digital (A/D) converter that converts an analog alternating current (AC) input signal having a given frequency into digital data, comprising: means for generating a noise signal which does not have any substantial energy at said given frequency; means for summing said analog AC input signal and said noise signal to produce a resultant signal that is coupled to an input of the A/D converter; clock means for generating periodic pulses at a first frequency coupled to said AD converter causing the latter to make A/D conversions in response to said pulses, the ratio of the rate of said periodic pulses to the bandwidth of said analog AC input signal being greater than 10; and the resultant signal produced by said summing means containing a signal component corresponding to said analog AC input signal which is converted by the A/D converter into a digital data representation.
Claim 39
Dependent Claim
34 words
The apparatus according to claim 33 wherein said generating means generates a noise signal that produces quantization noise at the digital data output from the A/D converter having an essentially uniform power spectral density.
Claim 40
Dependent Claim
15 words
The apparatus according to claim 33 wherein said generating means generates a Gaussian noise signal.
Claim 41
Dependent Claim
27 words
The apparatus according to claim 33 wherein said generating means generates a noise signal having an amplitude less than the maximum voltage range of the A/D converter.
Claim 42
Dependent Claim
27 words
The apparatus according to claim 36 wherein the amplitude of the noise signal is approximately 15 decibels less than the maximum voltage range of the A/D converter.
Claim 43
Dependent Claim
39 words
The apparatus according to claim 33 further comprising means for periodically sampling the amplitude of the analog AC input signal and storing the sampled amplitude, said stored amplitude of the analog AC input signal coupled to said summing means.
Claim 44
Dependent Claim
36 words
The apparatus according to claim 38 wherein said sampling means includes means for generating sampling pulses having a time duration of less than 0.5 times the reciprocal of the frequency of said analog AC input signal.
Claim 45
Dependent Claim
29 words
The apparatus according to claim 33 wherein the first frequency of said pulses generated by said clock means is less than the given frequency of said AC input signal.
Claim 46
Dependent Claim
78 words
The apparatus according to claim 33 wherein the A/D converter has a given threshold sensitivity and the magnitude of said AC input signal is less than said threshold sensitivity, said signal component corresponding to the AC input signal being converted by the A/D into digital data, whereby AC input signal having a magnitude less than said given threshold sensitivity of the A/D converter can be converted into digital data thereby extending the threshold sensitivity of the A/D converter.
Claim 47
Independent Claim
153 words
A method for extending the threshold sensitivity of an analog to digital (A/D) converter that converts an analog alternating current (AC) input signal having a given frequency into digital data comprising the steps of: generating a noise signal which does not have any substantial energy at said given frequency; summing the analog AC input signal and said noise signal to produce a resultant signal which contains a signal component corresponding to said AC input signal; coupling the resultant signal to the input of the A/D converter; generating periodic clock pulses at a first frequency which are coupled to said A/D converter and cause A/D conversions to be made in response to said pulses, the ratio of the rate of the clock pulses to the bandwidth of the analog AC input signal being greater than 10; and the A/D converter converting said signal component into digital data representative of said analog AC input signal.
Claim 48
Independent Claim
153 words
A method for extending the threshold sensitivity of an analog to digital (A/D) converter that converts an analog alternating current (AC) input signal having a given frequency into digital data comprising the steps of: generating a noise signal which does not have any substantial energy at said given frequency; summing the analog AC input signal and said noise signal to produce a resultant signal which contains a signal component corresponding to said AC input signal; coupling the resultant signal to the input of the A/D converter; generating periodic clock pulses at a first frequency which are coupled to said A/D converter and cause A/D conversions to be made in response to said pulses, the ratio of the rate of the clock pulses to the bandwidth of the analog AC input signal being greater than 10; and the A/D converter converting said signal component into digital data representative of said analog AC input signal.
Claim 49
Dependent Claim
39 words
The method according to claim 42 further comprising the steps of periodically sampling the amplitude of the analog AC input signal, storing the sampled amplitude, and summing the stored amplitude with the noise signal to produce said resultant signal.
Claim 50
Dependent Claim
44 words
The method according to claim 43 wherein said sampling step includes the step of generating sampling pulses that determine the duration of the sampling pulses, the sampling pulses being less than 0.5 times the reciprocal of the frequency of said analog AC input signal.
Claim 51
Dependent Claim
24 words
The method according to claim 42 wherein the first frequency of said pulses is less than the given frequency of said AC input signal.
Claim 52
Dependent Claim
54 words
The method according to claim 42 wherein said A/D converter has a given threshold sensitivity and the magnitude of said AC input signal is less than said threshold sensitivity, wherein said step of converting by the A/D converter of the signal component into digital data effectively extends the threshold sensitivity of the A/D converter.
Claim 53
Dependent Claim
171 words
In a communications receiver having a bandpass filter with a bandwidth which permits the passage of an analog radio frequency (RF) input signal having a frequency within a predetermined range of frequencies and an analog to digital (A/D) converter having a digital data output, the improvement comprising: means for generating a noise signal which does not have any substantial energy within said range of frequencies; means for summing said filtered analog RF input signal and said noise signal to produce a resultant signal that is coupled to an input of the A/D converter; clock means for generating periodic pulses at a first frequency coupled to the A/D converter causing the latter to make A/D conversions in response thereto, the ratio of the rate of said periodic pulses to the bandwidth of said analog AC input signal being greater than 10; and said summing means producing a resultant signal containing a signal component corresponding to said analog RF input signal which is converted by the A/D converter into a digital data representation.
Claim 54
Dependent Claim
171 words
In a communications receiver having a bandpass filter with a bandwidth which permits the passage of an analog radio frequency (RF) input signal having a frequency within a predetermined range of frequencies and an analog to digital (A/D) converter having a digital data output, the improvement comprising: means for generating a noise signal which does not have any substantial energy within said range of frequencies; means for summing said filtered analog RF input signal and said noise signal to produce a resultant signal that is coupled to an input of the A/D converter; clock means for generating periodic pulses at a first frequency coupled to the A/D converter causing the latter to make A/D conversions in response thereto, the ratio of the rate of said periodic pulses to the bandwidth of said analog AC input signal being greater than 10; and said summing means producing a resultant signal containing a signal component corresponding to said analog RF input signal which is converted by the A/D converter into a digital data representation.
Claim 55
Dependent Claim
34 words
The apparatus according to claim 47 wherein said generating means generates a noise signal that produces quantization noise at the digital data output from the A/D converter having an essentially uniform power spectral density.
Claim 56
Dependent Claim
15 words
The apparatus according to claim 47 wherein said generating means generates a Gaussian noise signal.
Claim 57
Dependent Claim
27 words
The apparatus according to claim 47 wherein said generating means generates a noise signal having an amplitude less than the maximum voltage range of the A/D converter.
Claim 58
Dependent Claim
27 words
The apparatus according to claim 50 wherein the amplitude of the noise signal is approximately 15 decibels less than the maximum voltage range of the A/D converter.
Claim 59
Dependent Claim
45 words
The apparatus according to claim 47 further comprising means for periodically sampling the amplitude of the filtered analog RF input signal and storing the sampled amplitude, said stored amplitude coupled to said summing means and summed with said noise signal to produce said resultant signal.
Claim 60
Dependent Claim
36 words
The apparatus according to claim 52 wherein said sampling means includes means for generating sampling pulses having a time duration of less than 0.5 times the reciprocal of the frequency of said analog RF input signal.
Claim 61
Dependent Claim
24 words
The apparatus according to claim 47 wherein the first frequency of said pulses is less than the given frequency of said AC input signal.
Claim 62
Dependent Claim
78 words
The receiver according to claim 47 wherein said A/D converter has a given threshold sensitivity and the magnitude of said AC input signal is less than said threshold sensitivity, said signal component corresponding to the AC input signal being converted by the A/D into digital data, whereby AC input signals having a magnitude less than said given threshold sensitivity of the A/D converter can be converted into digital data thereby extending the threshold sensitivity of the A/D converter.
Claim 63
Independent Claim
129 words
A method for converting an analog radio frequency (RF) signal having a given frequency into digital data comprising the steps of: bandpass filtering said analog RF signal; storing a first signal corresponding to an instantaneous magnitude of said filtered analog RF signal; generating a noise signal which does not have any substantial energy at said given frequency; summing said first signal and said noise signal to produce a resultant signal; coupling said resultant signal to an analog to digital (A/D) converter; generating periodic clock pulses at a first frequency which are coupled to said A/D converter and cause A/D conversions to be made in response to said pulses, the ratio of the rate of the clock pulses to the bandwidth of the analog RF signal being greater than 10.
Claim 64
Independent Claim
129 words
A method for converting an analog radio frequency (RF) signal having a given frequency into digital data comprising the steps of: bandpass filtering said analog RF signal; storing a first signal corresponding to an instantaneous magnitude of said filtered analog RF signal; generating a noise signal which does not have any substantial energy at said given frequency; summing said first signal and said noise signal to produce a resultant signal; coupling said resultant signal to an analog to digital (A/D) converter; generating periodic clock pulses at a first frequency which are coupled to said A/D converter and cause A/D conversions to be made in response to said pulses, the ratio of the rate of the clock pulses to the bandwidth of the analog RF signal being greater than 10.
Claim 65
Dependent Claim
31 words
The method according to claim 56 further comprising the step of periodically sampling the instantaneous magnitude of said analog RF signal and storing a first signal corresponding to said sampled magnitude.
Claim 66
Dependent Claim
36 words
The method according to claim 57 wherein said sampling step includes the step of generating sampling pulses having a time duration of less than 0.5 times the reciprocal of the frequency of said analog RF signal.
Claim 67
Dependent Claim
24 words
The method according to claim 56 wherein the first frequency of said pulses is less than the given frequency of said AC input signal.
Claim 68
Dependent Claim
51 words
The method according to claim 56 wherein said A/D converter has a given threshold sensitivity and the magnitude of said RF signal is less than said threshold sensitivity, wherein the converting by the A/D converter of the signal component into digital data effectively extends the threshold sensitivity of the A/D converter.
Claim 69
Dependent Claim
173 words
A digital zero-IF selectivity section circuit operating on a recovered input signal in a receiver device, comprising, in combination: clock means for providing a periodic clock signal; digital oscillator means, coupled to said clock means, for providing first and second digitized discrete-time signals, such that said first digitized discrete time signal leads said second digitized discrete time signal by 90 degrees in phase; means for digital quadrature mixing the input signal and said first and second digitized discrete time signals to provide first and second digitized output signals occupying a selected frequency band centered substantially at zero Hertz; and first and second digital filtering means, each comprising: a decomposed, internally multiplexed, filter section coupled to said digitized output signals; sample rate reducing means coupled to said decomposed filter section; a multiplierless digital filter section coupled to said sample rate reducing means; whereby, said first and second digital filtering means operate to selectively band-limit the frequency spectrum of said first and second digitized output signals thereby providing first and second filtered digitized output signals.
Claim 70
Dependent Claim
173 words
A digital zero-IF selectivity section circuit operating on a recovered input signal in a receiver device, comprising, in combination: clock means for providing a periodic clock signal; digital oscillator means, coupled to said clock means, for providing first and second digitized discrete-time signals, such that said first digitized discrete time signal leads said second digitized discrete time signal by 90 degrees in phase; means for digital quadrature mixing the input signal and said first and second digitized discrete time signals to provide first and second digitized output signals occupying a selected frequency band centered substantially at zero Hertz; and first and second digital filtering means, each comprising: a decomposed, internally multiplexed, filter section coupled to said digitized output signals; sample rate reducing means coupled to said decomposed filter section; a multiplierless digital filter section coupled to said sample rate reducing means; whereby, said first and second digital filtering means operate to selectively band-limit the frequency spectrum of said first and second digitized output signals thereby providing first and second filtered digitized output signals.
Claim 71
Dependent Claim
130 words
The circuit of claim 61, wherein said decomposed, internally multiplexed filter section comprises: means for generating a second periodic clock signal wherein said second clock signal has a period approximately equal to at least twice the period of said first clock signal; demultiplexing means, coupled to said digitized output signals for demultiplexing same into at least two demultiplexed signals; first filtering means for filtering said demultiplexed signals providing at least two filtered demultiplexed signals; multiplexing means for multiplexing said filtered demultiplexed signals into a multiplexed signal which represents a selectively band-limited portion of said input signal; and second filtering means coupled to said first clock signal and said multiplexed signal for providing a combined and filtered multiplexed output signal which represents a selectively band-limited portion of said digitized output signals.
Claim 72
Dependent Claim
183 words
The circuit of claim 61, wherein each of said multiplierless digital filter sections comprise: first binary summing means coupled to an input signal and a second binary delayed signal for providing a first binary sum signal; first binary shifting means coupled to said first binary sum signal for providing a shifted first binary sum signal; second binary summing means coupled to said shifted first sum signal and a first binary delayed signal for providing a second binary sum signal; first binary storage means coupled to said second binary sum signal for providing said first binary delayed signal; third binary summing means coupled to said first binary delayed signal and said second delayed binary signal for providing a third binary sum signal; second binary shifting means coupled to said third binary sum signal for providing a shifted third binary sum signal; fourth binary summing means coupled to said shifted third binary sum signal and said second binary delayed signal for providing a fourth binary sum signal; second binary storage means coupled to said fourth binary sum signal for providing said second binary delayed signal.
Claim 73
Dependent Claim
17 words
The circuit of claim 63, wherein said second binary delayed signal comprises th digital filter output signal.
Claim 74
Dependent Claim
258 words
A digital zero-IF selectivity section for operating on a received input signal in a receiver, comprising, in combination; clock means for providing at least a first and second periodic clock signal; digital oscillator means, coupled to said clock means, for providing first and second digitized discrete-time signals such that said first digitized discrete-time signal leads said second digitized discrete time signal by 90 degrees in phase; means for digital quadrature mixing the input signal and said first and second digitized signals for providing first and second digitized output signals such that said first and second digitized output signals such that said first and second digitized output signals occupy a selected frequency band centered substantially at zero Hertz; first and second digital filtering means, each of said first and second digital filtering means comprising at least one digital filtering section coupled to a sample rate reducing means, and each of said first and second digital filtering means being coupled to said clock means for providing first and second filtered digitized output signals; multiplexing means coupled to said first and second digital filter means to provide a multiplex output signal; third digital filtering means, coupled to said multiplex means, comprising at least one digital filtering section, coupled to said clock means, for providing a selected order filter and to provide a filtered multiplex signal; demultiplexing means coupled to said clock means and said filtered multiplex signal for providing first and second output signals such that said first and second output signal occupy a frequency band substantially centered at zero Hertz.
Claim 75
Dependent Claim
258 words
A digital zero-IF selectivity section for operating on a received input signal in a receiver, comprising, in combination; clock means for providing at least a first and second periodic clock signal; digital oscillator means, coupled to said clock means, for providing first and second digitized discrete-time signals such that said first digitized discrete-time signal leads said second digitized discrete time signal by 90 degrees in phase; means for digital quadrature mixing the input signal and said first and second digitized signals for providing first and second digitized output signals such that said first and second digitized output signals such that said first and second digitized output signals occupy a selected frequency band centered substantially at zero Hertz; first and second digital filtering means, each of said first and second digital filtering means comprising at least one digital filtering section coupled to a sample rate reducing means, and each of said first and second digital filtering means being coupled to said clock means for providing first and second filtered digitized output signals; multiplexing means coupled to said first and second digital filter means to provide a multiplex output signal; third digital filtering means, coupled to said multiplex means, comprising at least one digital filtering section, coupled to said clock means, for providing a selected order filter and to provide a filtered multiplex signal; demultiplexing means coupled to said clock means and said filtered multiplex signal for providing first and second output signals such that said first and second output signal occupy a frequency band substantially centered at zero Hertz.
Claim 76
Dependent Claim
312 words
A digital zero-If selectivity section for operating on a recovered input signal in a receiver, comprising, in combination: clock means for providing a periodic first clock signal; means for dividing the frequency of said clock signal to provide a second clock signal; digital oscillator means, coupled to said clock means, for providing first and second digitized discrete-time signals such that said first digitized discrete-time signal leads said second digitized discrete time signal by 90 degrees in phase; means for digital quadrature mixing the input signal and said first and second digitized output signals such that said first and second digitized output signals occupy a selected frequency band centered substantially at zero Hertz; first and second digital filtering section means respectively coupled to receive said first and second digitized output signals and each of said first and second digital filtering section means being coupled to said clock means for providing first and second filtered digitized output signals; first and second data sampling rate reducer means respectively coupled to said first and second filtered digitized output signals for providing first and second reduced rate data signals; multiplexing means coupled to said first and second reduced rate data signals to provide a multiplex output signal; third digital filtering section means coupled to said second clock signal and said multiplex output signal to provide a first filtered multiplex signal; fourth digital filtering section means coupled to said second clock signal and said first filtered multiplex signal to provide a second filtered multiplex signal; fifth digital filtering section means coupled to said second clock signal and said second filtered multiplex signal to provide a third filtered multiplex signal; and demultiplexing means coupled to said second clock signal and said third filtered multiplex signal for providing first and second output signals such that said first and second output signal occupy a frequency band substantially centered at zero Hertz.
Claim 77
Dependent Claim
312 words
A digital zero-If selectivity section for operating on a recovered input signal in a receiver, comprising, in combination: clock means for providing a periodic first clock signal; means for dividing the frequency of said clock signal to provide a second clock signal; digital oscillator means, coupled to said clock means, for providing first and second digitized discrete-time signals such that said first digitized discrete-time signal leads said second digitized discrete time signal by 90 degrees in phase; means for digital quadrature mixing the input signal and said first and second digitized output signals such that said first and second digitized output signals occupy a selected frequency band centered substantially at zero Hertz; first and second digital filtering section means respectively coupled to receive said first and second digitized output signals and each of said first and second digital filtering section means being coupled to said clock means for providing first and second filtered digitized output signals; first and second data sampling rate reducer means respectively coupled to said first and second filtered digitized output signals for providing first and second reduced rate data signals; multiplexing means coupled to said first and second reduced rate data signals to provide a multiplex output signal; third digital filtering section means coupled to said second clock signal and said multiplex output signal to provide a first filtered multiplex signal; fourth digital filtering section means coupled to said second clock signal and said first filtered multiplex signal to provide a second filtered multiplex signal; fifth digital filtering section means coupled to said second clock signal and said second filtered multiplex signal to provide a third filtered multiplex signal; and demultiplexing means coupled to said second clock signal and said third filtered multiplex signal for providing first and second output signals such that said first and second output signal occupy a frequency band substantially centered at zero Hertz.
Claim 78
Dependent Claim
82 words
The circuit of claims 61, 65 or 66, wherein said digital oscillator means further comprises: binary addressing means having an input port for receiving a frequency information signal and an additional input port coupled to said clock means to provide a binary address signal; binary storage means coupled to said binary addressing means for providing a plurality of stored binary signals; and combining means constructed and arranged to combine said stored binary signals for providing said first and second digitized discrete-time signals.
Claim 79
Dependent Claim
27 words
The circuit of claim 67, wherein said binary addressing means includes a first and second binary storage means comprised of a plurality of single bit storage means.
Claim 80
Dependent Claim
12 words
The circuit of claim 67, wherein said binary storage means comprises read-only-memory.
Claim 81
Dependent Claim
49 words
The circuit of claims 61, 65 or 66, wherein said digital quadrature mixing means further comprises: first and second discrete mixing means each coupled to said input signal and a respective one of said first and second digitized discrete-time signals to provide said first and second digitized output signals.
Claim 82
Dependent Claim
15 words
The circuit of claim 70, wherein said first and second mixing means comprise digital multipliers.
Claim 83
Dependent Claim
132 words
A digital zero-IF selectivity section circuit operating on a first and second input signal in a transmitter device, comprising, in combination: clock means for providing a periodic clock signal; digital oscillator means, coupled to said clock means, for providing first and second digitized discrete-time signals such that said first digitized discrete time signal leads said second digitized discrete time signal by 90 degrees in phase; first and second digital filtering means, coupled to the first and second input signals and said clock means, for selectively band-limiting the frequency spectrum of said first and second input signals thereby providing first and second filtered input signals; and means for digital quadrature mixing said first and second filtered input signals and said first and second digitized signals to provide first and second digitized output signals.
Claim 84
Dependent Claim
132 words
A digital zero-IF selectivity section circuit operating on a first and second input signal in a transmitter device, comprising, in combination: clock means for providing a periodic clock signal; digital oscillator means, coupled to said clock means, for providing first and second digitized discrete-time signals such that said first digitized discrete time signal leads said second digitized discrete time signal by 90 degrees in phase; first and second digital filtering means, coupled to the first and second input signals and said clock means, for selectively band-limiting the frequency spectrum of said first and second input signals thereby providing first and second filtered input signals; and means for digital quadrature mixing said first and second filtered input signals and said first and second digitized signals to provide first and second digitized output signals.
Claim 85
Dependent Claim
79 words
The circuit of claim 72, wherein said digital oscillator means further comprises: binary addressing means having an input port for receiving a frequency information signal and an additional input port coupled to said clock means to provide a binary address signal; binary storage means coupled to said binary addressing means for providing a plurality of stored binary signals; and combining means constructed and arranged to combine said stored binary signals for providing said first and second digitized discrete-time signals.
Claim 86
Dependent Claim
27 words
The circuit of claim 73, wherein said binary addressing means includes a first and second binary storage means comprised of a plurality of single bit storage means.
Claim 87
Dependent Claim
12 words
The circuit of claim 73, wherein said binary storage means comprises read-only-memory.
Claim 88
Dependent Claim
50 words
The circuit of claim 72, wherein said digital quadrature mixing means further comprises: first and second discrete mixing means each coupled respectively to said first and second input signals and a respective one of said first and second digitized discrete-time signals to provide said first and second digitized output signals.
Claim 89
Dependent Claim
15 words
The circuit of claim 76, wherein said first and second mixing means comprise digital multipliers.
Claim 90
Dependent Claim
48 words
The circuit of claim 72, wherein each of said first and second digital filtering means further comprises: at least two digital filter sections cascaded together for achieving a selected order digital filter and intercoupled by sampling rate increasing means, for reducing the operating speed of subsequent logic sections.
Claim 91
Dependent Claim
15 words
The circuit of claim 78, wherein said digital filter sections do not employ digital multipliers.
Claim 92
Dependent Claim
181 words
The circuit of claim 79, wherein each of said filter further comprises: first binary summing means coupled to an input signal and a second binary delayed signal for providing a first binary sum signal; first binary shifting means coupled to said first binary sum signal for providing a shifted first binary sum signal; second binary summing means coupled to said shifted first sum signal and a first binary delayed signal for providing a second binary sum signal; first binary storage means coupled to said second binary sum signal for providing said first binary delayed signal; third binary summing means coupled to said first binary delayed signal and said second shifted binary signal for providing a third binary sum signal; second binary shifting means coupled to said third binary sum signal for providing a shifted third binary sum signal; fourth binary summing means coupled to said shifted third binary sum signal and said second binary delayed signal for providing a fourth binary sum signal; second binary storage means coupled to said fourth binary sum signal for providing said second binary delayed signal.
Claim 93
Dependent Claim
17 words
The circuit of claim 80 wherein said second binary delayed signal comprises the digital filter output signal.
Claim 94
Dependent Claim
123 words
The circuit of claim 78, which includes: first and second periodic clock signal means wherein said second clock signal has a period approximately equal to at least twice the period of said first clock signal; demultiplexing means, coupled to the input signal for demultiplexing the input signal into at least two demultiplexed signals; first filtering means for filtering said demultiplexed signals providing at least two filtered demultiplexed signals; multiplexing means, for multiplexing said filtered demultiplexed signals into a multiplexed signal which represents a selectively band-limited portion of said input signal; and second filtering means coupled to said first clock signal and said multiplexed signal for providing a combined and filtered multiplexed output signal which represents a selectively band-limited portion of said input signal.
Claim 95
Dependent Claim
240 words
In a receiver for receiving and periodically presenting a received digital input signal to an intermediate frequency section, the improvement comprising: clock means for providing a periodic clock signal; a digital oscillator means, coupled to clock means, for providing first and second digitized discrete-time signals such that said first digitized discrete-time signal leads said second digitized discrete time signal by 90 degrees in phase; means for digital quadrature mixing the digital input signal and said first and second digitized discrete time signals to provide first and second digitized output signals occupying a selected frequency band centered substantially at zero hertz; and first and second digital filtering means, coupled to said digital quadrature mixing means and to said clock means, for selectively band-limiting the frequency spectrum of said first and second digitized output signals providing first and second filtered digitized output signals, each of said digital filtering means comprising: at least one digital filtering section intercoupled by a sample rate reducing means; multiplexing means coupled to said digital filter sections to provide a multiplex output signal; third digital filtering means, coupled to said multiplex means, comprising at least one digital filtering section for providing a selected order filter and to provide a filtered multiplex signal; demultiplexing means coupled to said clock means and said filtered multiplex signal for providing first and second output signals such that said first and second output signal occupy a frequency band substantially centered at zero Hertz.
Claim 96
Dependent Claim
240 words
In a receiver for receiving and periodically presenting a received digital input signal to an intermediate frequency section, the improvement comprising: clock means for providing a periodic clock signal; a digital oscillator means, coupled to clock means, for providing first and second digitized discrete-time signals such that said first digitized discrete-time signal leads said second digitized discrete time signal by 90 degrees in phase; means for digital quadrature mixing the digital input signal and said first and second digitized discrete time signals to provide first and second digitized output signals occupying a selected frequency band centered substantially at zero hertz; and first and second digital filtering means, coupled to said digital quadrature mixing means and to said clock means, for selectively band-limiting the frequency spectrum of said first and second digitized output signals providing first and second filtered digitized output signals, each of said digital filtering means comprising: at least one digital filtering section intercoupled by a sample rate reducing means; multiplexing means coupled to said digital filter sections to provide a multiplex output signal; third digital filtering means, coupled to said multiplex means, comprising at least one digital filtering section for providing a selected order filter and to provide a filtered multiplex signal; demultiplexing means coupled to said clock means and said filtered multiplex signal for providing first and second output signals such that said first and second output signal occupy a frequency band substantially centered at zero Hertz.
Claim 97
Dependent Claim
469 words
A digital zero-IF selectivity section circuit operating on a recovered input signal in a receiver device comprising, in combination: clock means for providing a first and second periodic clock signal, such that said second clock signal has a period approximately twice that of said first clock signal; digital oscillator means, coupled to said first clock signal, for providing first and second digitized discrete-time signals, such that said first digitized discrete time signal leads said second digitized discrete time signal by 90 degrees in phase; means for digital quadrature mixing the input signal and said first and second digitized discrete time signals to provide first and second digitized output signals occupying a selected frequency band centered substantially at zero Hertz; and first and second digital filtering means, each comprising: at least two digital filter sections cascaded together for achieving a selected order digital filter, at least the first section comprising: demultiplexing means, coupled to said digitized output signals for demultiplexing same into at least two demultiplexed signals; first filtering means, coupled to said second clock signal, for filtering said demultiplexed signals providing at least two filtered demultiplexed signals; multiplexing means for multiplexing said filtered demultiplexed signals into a multiplexed signal which represents a selectively band-limited portion of said input signal; and second filtering means coupled to said first clock signal and said multiplexed signal for providing a combined and filtered multiplexed output signal; sample rate reducing means, coupled at least between the first and second filter sections, for reducing the operating speed of subsequent filter sections, each of said subsequent filter sections comprising: first binary summing means coupled to an input signal and a second binary delayed signal for providing a first binary sum signal; first binary shifting means coupled to said first binary sum signal for providing a shifted first binary sum signal; second binary summing means coupled to said shifted first sum signal and a first binary delayed signal for providing a second binary sum signal; first binary storage means coupled to said second binary sum signal for providing said first binary delayed signal; third binary summing means coupled to said first binary delayed signal and said second delayed binary signal for providing a third binary sum signal; second binary shifting means coupled to said third binary sum signal for providing a shifted third binary sum signal; fourth binary summing means coupled to said shifted third binary sum signal and said second binary delayed signal for providing a fourth binary sum signal; second binary storage means coupled to said fourth binary sum signal for providing said second binary delayed signal comprising a filtered digitized output signal; whereby, said first and second digital filtering means operate to selectively band-limit the frequency spectrum of said first and second digitized output signals thereby providing first and second filtered digitized output signals.
Claim 98
Dependent Claim
469 words
A digital zero-IF selectivity section circuit operating on a recovered input signal in a receiver device comprising, in combination: clock means for providing a first and second periodic clock signal, such that said second clock signal has a period approximately twice that of said first clock signal; digital oscillator means, coupled to said first clock signal, for providing first and second digitized discrete-time signals, such that said first digitized discrete time signal leads said second digitized discrete time signal by 90 degrees in phase; means for digital quadrature mixing the input signal and said first and second digitized discrete time signals to provide first and second digitized output signals occupying a selected frequency band centered substantially at zero Hertz; and first and second digital filtering means, each comprising: at least two digital filter sections cascaded together for achieving a selected order digital filter, at least the first section comprising: demultiplexing means, coupled to said digitized output signals for demultiplexing same into at least two demultiplexed signals; first filtering means, coupled to said second clock signal, for filtering said demultiplexed signals providing at least two filtered demultiplexed signals; multiplexing means for multiplexing said filtered demultiplexed signals into a multiplexed signal which represents a selectively band-limited portion of said input signal; and second filtering means coupled to said first clock signal and said multiplexed signal for providing a combined and filtered multiplexed output signal; sample rate reducing means, coupled at least between the first and second filter sections, for reducing the operating speed of subsequent filter sections, each of said subsequent filter sections comprising: first binary summing means coupled to an input signal and a second binary delayed signal for providing a first binary sum signal; first binary shifting means coupled to said first binary sum signal for providing a shifted first binary sum signal; second binary summing means coupled to said shifted first sum signal and a first binary delayed signal for providing a second binary sum signal; first binary storage means coupled to said second binary sum signal for providing said first binary delayed signal; third binary summing means coupled to said first binary delayed signal and said second delayed binary signal for providing a third binary sum signal; second binary shifting means coupled to said third binary sum signal for providing a shifted third binary sum signal; fourth binary summing means coupled to said shifted third binary sum signal and said second binary delayed signal for providing a fourth binary sum signal; second binary storage means coupled to said fourth binary sum signal for providing said second binary delayed signal comprising a filtered digitized output signal; whereby, said first and second digital filtering means operate to selectively band-limit the frequency spectrum of said first and second digitized output signals thereby providing first and second filtered digitized output signals.
Claim 99
Independent Claim
121 words
An apparatus for substantially digitally processing a wideband analog signal containing a desired narrow band analog signal, comprising: (a) means, including coupling means and filter means for receiving and filtering a wideband analog signal containing a desired narrowband analog signal; (b) digitizing means, coupled to said filter means, for periodically sampling and converting said wideband analog signal to a sampled wideband digital signal; (c) digital means, coupled to said digitizing means, for selecting the desired sampled narrowband digital signal from the sampled wideband digital signal, wherein said digital means includes a digital quadrature oscillator means, a digital quadrature multiplier/mixer means, a digital quadrature narrowband lowpass filter means, and means for programmably controlling the bandwidth of said digital quadrature lowpass filter means.
Claim 100
Independent Claim
121 words
An apparatus for substantially digitally processing a wideband analog signal containing a desired narrow band analog signal, comprising: (a) means, including coupling means and filter means for receiving and filtering a wideband analog signal containing a desired narrowband analog signal; (b) digitizing means, coupled to said filter means, for periodically sampling and converting said wideband analog signal to a sampled wideband digital signal; (c) digital means, coupled to said digitizing means, for selecting the desired sampled narrowband digital signal from the sampled wideband digital signal, wherein said digital means includes a digital quadrature oscillator means, a digital quadrature multiplier/mixer means, a digital quadrature narrowband lowpass filter means, and means for programmably controlling the bandwidth of said digital quadrature lowpass filter means.
Claim 101
Dependent Claim
15 words
The apparatus as recited in claim 85 wherein said filter means is an RLC filter.
Claim 102
Dependent Claim
16 words
The apparatus as recited in claim 85 wherein said filter means is a transmission line filter.
Claim 103
Dependent Claim
15 words
The apparatus as recited in claim 85 wherein said filter means is a crystal filter.
Claim 104
Dependent Claim
18 words
The apparatus as recited in claim 85 wherein said filter means is a Surface Acoustic Wave (SAW) filter.
Claim 105
Dependent Claim
31 words
The apparatus as recited in claim 85 wherein said digitizing means is a flash A/D converter sampling at a rate at least twice the highest frequency of the wideband analog signal.
Claim 106
Dependent Claim
35 words
The apparatus as recited in claim 85 wherein said digitizing means is a sample-and-hold circuit and an A/D converter sampling and converting at a rate substantially higher than the bandwidth of the wideband analog signal.
Claim 107
Dependent Claim
26 words
The apparatus as recited in claim 85 wherein said digital means includes a digital oscillator means, a digital multiplier/mixer means, and a digital narrowband filter means.
Claim 108
Dependent Claim
25 words
The apparatus as recited in claim 92 wherein said digital oscillator means contains means for programmably controlling the operating frequency of said digital oscillator means.
Claim 109
Dependent Claim
22 words
The apparatus as recited in claim 92 wherein said digital filter contains means for programmably controlling the bandwidth of said digital filter.
Claim 110
Dependent Claim
24 words
The apparatus as recited in claim 92 wherein said apparatus includes decimating means for substantially reducing the sampling rate of said wideband digital signal.
Claim 111
Dependent Claim
14 words
The apparatus as recited in claim 92 wherein said digital narrowband filter is multiplierless.
Claim 112
Dependent Claim
27 words
The apparatus as recited in claim 85 wherein said digital quadrature oscillator means contains means for programmably controlling the operating frequency of said digital quadrature oscillator means.
Claim 113
Dependent Claim
24 words
The apparatus as recited in claim 85 wherein said apparatus includes decimating means for substantially reducing the sampling rate of said wideband digital signal.
Claim 114
Dependent Claim
15 words
The apparatus as recited in claim 85 wherein said digital quadrature lowpass filter is multiplierless.
Claim 115
Dependent Claim
19 words
The apparatus as recited in claim 85 wherein said digital processing means comprises a general purpose digital signal processor.
Claim 116
Dependent Claim
23 words
The apparatus as recited in claim 85 wherein said digital processing means further includes means for additional digital filtering and sampling rate reduction.
Claim 117
Dependent Claim
19 words
The apparatus as recited in claim 85 wherein said digital processing means further includes means for FM demodulation processing.
Claim 118
Dependent Claim
19 words
The apparatus as recited in claim 85 wherein said digital processing means further includes means for AM demodulation processing.
Claim 119
Dependent Claim
19 words
The apparatus as recited in claim 85 wherein said digital processing means further includes means for SSB demodulation processing.
Claim 120
Dependent Claim
21 words
The apparatus as recited in claim 85 wherein said digital processing means further includes means for demodulation of angle modulated signals.
Claim 121
Dependent Claim
20 words
The apparatus as recited in claim 85 wherein said digital processing means further includes means for Quadrature AM demodulation processing.
Claim 122
Independent Claim
82 words
A method for substantially digitally processing a wideband analog signal containing a desired narrowband analog signal, comprising the steps of: (a) receiving and filtering a wideband analog signal containing a desired narrowband analog signal; (b) periodically sampling and converting said wideband analog signal to a sampled wideband digital signal; (c) selecting the desired sampled narrowband digital signal from the sampled wideband digital signal; and (d) programmably controlling the bandwidth of the sampled narrowband digital signal: (e) demodulating said sampled narrowband digital signal.
Claim 123
Independent Claim
82 words
A method for substantially digitally processing a wideband analog signal containing a desired narrowband analog signal, comprising the steps of: (a) receiving and filtering a wideband analog signal containing a desired narrowband analog signal; (b) periodically sampling and converting said wideband analog signal to a sampled wideband digital signal; (c) selecting the desired sampled narrowband digital signal from the sampled wideband digital signal; and (d) programmably controlling the bandwidth of the sampled narrowband digital signal: (e) demodulating said sampled narrowband digital signal.
Claim 124
Dependent Claim
28 words
The method as recited in claim 107 wherein said sampling and converting step occurs at a rate at least twice the highest frequency of the wideband analog signal.
Claim 125
Dependent Claim
35 words
The method as recited in claim 107 wherein said sampling and converting step further comprises the individual steps of sampling and converting at a rate substantially higher than the bandwidth of the wideband analog signal.
Claim 126
Dependent Claim
55 words
The method as recited in claim 107 wherein said selecting step further comprises the steps of generating a digital local oscillator signal, multiplying the digital local oscillator signal by the sampled wideband digital signal to produce a sampled product signal, and digital narrowband filtering the sampled product signal to produce the sampled narrowband digital signal.
Claim 127
Dependent Claim
22 words
The method as recited in claim 110 further including the step of programmably controlling the frequency of said digital local oscillator signal.
Claim 128
Dependent Claim
25 words
The method as recited in claim 110 wherein said steps further include the step of programmably controlling the bandwidth of said sampled narrow-band digital signal.
Claim 129
Dependent Claim
25 words
The method as recited in claim 110 wherein said steps further comprise the step of substantially reducing the sampling rate of said sampled product signal.
Claim 130
Dependent Claim
19 words
The method as recited in claim 110 wherein said digitally narrowband filtering step comprises filtering with multiplierless digital filters.
Claim 131
Dependent Claim
57 words
The method as recited in claim 107 wherein said selecting step further comprises the steps of generating a digital quadrature oscillator signal, quadrature multiplying the digital quadrature oscillator signal by the sampled wideband digital signal to produce a sampled product signal, and digital quadrature lowpass filtering the sampled product signal to produce the sampled narrow-band digital signal.
Claim 132
Dependent Claim
23 words
The method as recited in claim 115, further including the step of programmably controlling the operating frequency of said digital quadrature oscillator signal.
Claim 133
Dependent Claim
25 words
The method as recited in claim 115 wherein said steps further include the step of substantially reducing the sampling rate of the sampled product signal.
Claim 134
Dependent Claim
20 words
The method as recited in claim 115 wherein said digital quadrature low-pass filtering step comprises filtering with mulitplierless digital filters.
Claim 135
Dependent Claim
16 words
The method as recited in claim 107 wherein said step of demodulation is FM demodulation processing.
Claim 136
Dependent Claim
15 words
The method as recited in claim 111 wherein said demodulating step is AM demodulation processing.
Claim 137
Dependent Claim
15 words
The method as recited in claim 107 wherein said demodulating step is SSB demodulation processing.
Claim 138
Dependent Claim
15 words
The method as recited in claim 107 wherein said demodulating step is angle demodulation processing.
Claim 139
Dependent Claim
16 words
The method as recited in claim 107 wherein said demodulating step is Quadrature AM demodulation processing.
Claim 140
Independent Claim
117 words
An apparatus for digitally processing a wideband radio frequency (RF) signal containing a desired narrowband signal, comprising: (a) means, including antenna means for receiving (RF) signals containing said wideband (RF) signal; (b) filter means, coupled to said antenna means, for filtering said wideband (RF) signal; (c) digitizing means, coupled to said filter means, for periodically sampling and converting said wideband RF signal to a sampled wideband digital signal; (d) digital means, coupled to said digitizing means, for selected the desired sampled narrowband signal from the sampled wideband digital signal; and (e) digital processing means for demodulating said sampled narrowband digital signal wherein said digital processing means further includes means for additional digital filtering and sampling rate reduction.
Claim 141
Independent Claim
117 words
An apparatus for digitally processing a wideband radio frequency (RF) signal containing a desired narrowband signal, comprising: (a) means, including antenna means for receiving (RF) signals containing said wideband (RF) signal; (b) filter means, coupled to said antenna means, for filtering said wideband (RF) signal; (c) digitizing means, coupled to said filter means, for periodically sampling and converting said wideband RF signal to a sampled wideband digital signal; (d) digital means, coupled to said digitizing means, for selected the desired sampled narrowband signal from the sampled wideband digital signal; and (e) digital processing means for demodulating said sampled narrowband digital signal wherein said digital processing means further includes means for additional digital filtering and sampling rate reduction.
Claim 142
Dependent Claim
15 words
The apparatus as recited in claim 124 wherein said filter means is an RLC filter.
Claim 143
Dependent Claim
16 words
The apparatus as recited in claim 124 wherein said filter means is a transmission line filter.
Claim 144
Dependent Claim
15 words
The apparatus as recited in claim 124 wherein said filter means is a crystal filter.
Claim 145
Dependent Claim
18 words
The apparatus as recited in claim 124 wherein said filter means is a Surface Acoustic Wave (SAW) filter.
Claim 146
Dependent Claim
31 words
The apparatus as recited in claim 124 wherein said digitizing means is a flash A/D converter sampling at a rate at least twice the highest frequency of the wideband RF signal.
Claim 147
Dependent Claim
35 words
The apparatus as recited in claim 124 wherein said digitizing means is a sample-and-hold circuit and an A/D converter sampling and converting at a rate substantially higher than the bandwidth of the wideband RF signal.
Claim 148
Dependent Claim
23 words
The apparatus as recited in claim 124 wherein said digital means includes a digital oscillator, a digital multiplier/mixer, and a digital narrowband filter.
Claim 149
Dependent Claim
23 words
The apparatus as recited in claim 131 wherein said digital oscillator contains means for programmably controlling the operating frequency of said digital oscillator.
Claim 150
Dependent Claim
22 words
The apparatus as recited in claim 131 wherein said digital filter contains means for programmably controlling the bandwidth of said digital filter.
Claim 151
Dependent Claim
25 words
The apparatus as recited in claim 131 wherein said apparatus includes decimating means for substantially reducing the sampling rate of the sampled wide-band digital signal.
Claim 152
Dependent Claim
14 words
The apparatus as recited in claim 131 wherein said digital narrowband filter is multiplierless.
Claim 153
Dependent Claim
28 words
The apparatus as recited in claim 124 wherein said digital means includes a digital quadrature oscillator, a digital quadrature multiplier/mixer, and a digital quadrature narrowband low pass filter.
Claim 154
Dependent Claim
25 words
The apparatus as recited in claim 136 wherein said digital quadrature oscillator contains means for programmably controlling the operating frequency of said digital quadrature oscillator.
Claim 155
Dependent Claim
28 words
The apparatus as recited in claim 136, wherein said digital quadrature narrowband lowpass filter contains means for programmably controlling the bandwidth of said digital quadrature narrowband lowpass filter.
Claim 156
Dependent Claim
25 words
The apparatus as recited in claim 136 wherein said apparatus includes decimating means for substantially reducing the sampling rate of the sampled wide-band digital signal.
Claim 157
Dependent Claim
15 words
The apparatus as recited in claim 136 wherein said digital quadrature lowpass filter is multiplierless.
Claim 158
Dependent Claim
19 words
The apparatus as recited in claim 124 wherein said digital processing means comprises a general purpose digital signal processor.
Claim 159
Dependent Claim
19 words
The apparatus as recited in claim 124 wherein said digital processing means further includes means for FM demodulation processing.
Claim 160
Dependent Claim
19 words
The apparatus as recited in claim 124 wherein said digital processing means further includes means for AM demodulation processing.
Claim 161
Dependent Claim
19 words
The apparatus as recited in claim 124 wherein said digital processing means further includes means for SSB demodulation processing.
Claim 162
Dependent Claim
21 words
The apparatus as recited in claim 124 wherein said digital processing means further includes means for demodulation of angle modulated signals.
Claim 163
Dependent Claim
20 words
The apparatus as recited in claim 124 wherein said digital processing means further includes means for Quadrature AM demodulation processing.
Claim 164
Independent Claim
126 words
A method for substantially digitally processing a wideband radio frequency (RF) signal containing a desired narrowband signal, comprising the steps of: (a) receiving (RF) signals containing said wideband RF signal; (b) filtering said wideband RF signal; (c) periodically sampling and converting said filtered wideband (RF) signal to a sampled wideband digital signal; (c) selecting the desired sampled narrowband digital signal from the sampled wideband digital signal by generating a digital quadrature local oscillator signal, quadrature multiplying the quadrature local oscillator signal by the sampled wideband digital signal to produce a product signal, digital quadrature narrowband lowpass filtering the product signal to produce the sampled narrowband digital signal, and programmably controlling the bandwidth of said sampled narrowband digital signal; (d) digitally demodulating said sampled narrowband digital signal.
Claim 165
Independent Claim
126 words
A method for substantially digitally processing a wideband radio frequency (RF) signal containing a desired narrowband signal, comprising the steps of: (a) receiving (RF) signals containing said wideband RF signal; (b) filtering said wideband RF signal; (c) periodically sampling and converting said filtered wideband (RF) signal to a sampled wideband digital signal; (c) selecting the desired sampled narrowband digital signal from the sampled wideband digital signal by generating a digital quadrature local oscillator signal, quadrature multiplying the quadrature local oscillator signal by the sampled wideband digital signal to produce a product signal, digital quadrature narrowband lowpass filtering the product signal to produce the sampled narrowband digital signal, and programmably controlling the bandwidth of said sampled narrowband digital signal; (d) digitally demodulating said sampled narrowband digital signal.
Claim 166
Dependent Claim
28 words
The method as recited in claim 147 wherein said sampling and converting step occurs at a rate at least twice the highest frequency of the wideband RF signal.
Claim 167
Dependent Claim
35 words
The method as recited in claim 147 wherein said sampling and converting step further comprises the individual steps of sampling and converting at a rate substantially higher than the bandwidth of the wideband RF signal.
Claim 168
Dependent Claim
55 words
The method as recited in claim 147 wherein said selecting step further includes the steps of generating a digital local oscillator signal, multiplying the digital local oscillator signal by the sampled wideband digital signal to produce a sampled product signal, and digital narrowband filtering the sampled product signal to produce the sampled narrow-band digital signal.
Claim 169
Dependent Claim
26 words
The method as recited in claim 150 wherein said steps further include the step of programmably controlling the operating frequency of said digital local oscillator signal.
Claim 170
Dependent Claim
25 words
The method as recited in claim 150 wherein said steps further include the step of programmably controlling the bandwidth of said sampled narrow-band digital signal.
Claim 171
Dependent Claim
26 words
The method as recited in claim 150 wherein said steps further comprise the step of substantially reducing the sampling rate of said sampled wideband digital signal.
Claim 172
Dependent Claim
18 words
The method as recited in claim 150 wherein said low-pass filtering step comprises filtering with multiplierless digital filters.
Claim 173
Dependent Claim
23 words
The method as recited in claim 147 further including the step of programmably controlling the operating frequency of said quadrature local oscillator signal.
Claim 174
Dependent Claim
26 words
The method as recited in claim 147 wherein said steps further includes the step of substantially reducing the sampling rate of said sampled wideband digital signal.
Claim 175
Dependent Claim
20 words
The digital method as recited in claim 147 wherein said quadrature lowpass filtering step comprises filtering with multiplierless digital filters.
Claim 176
Dependent Claim
16 words
The digital method as recited in claim 147 wherein said demodulating step comprises FM demodulation processing.
Claim 177
Dependent Claim
16 words
The digital method as recited in claim 147 wherein said demodulating step comprises AM demodulation processing.
Claim 178
Dependent Claim
16 words
The digital method as recited in claim 147 wherein said demodulating step comprises SSB demodulation processing.
Claim 179
Dependent Claim
16 words
The digital method as recited in claim 147 wherein said demodulating step comprises angle demodulation processing.
Claim 180
Dependent Claim
17 words
The digital method as recited in claim 147 wherein said demodulating step comprises Quadrature AM demodulation processing.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-08 | 1993-07-10 | 1994-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-08 | 1997-07-10 | 1998-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-08 | 2001-07-10 | 2002-01-09 | $7700.00 | Window Closed / Lapsed |