Digital integrating/auto-correlator apparatus

Claim 2

A digital integrating/auto-correlator apparatus comprising in combination: switching means for receiving a first and second signal, a filter means for receiving the output from said switching means, said filter means providing a filtered output signal, a sample and hold means connected to said filter means to receive said filtered output signal, said sample and hold means receiving a sample control signal, said sample and hold means providing a time invariant output signal, an A/D converter means connected to said sample and hold means to receive said output signal therefrom, said A/D converter means receiving a convert control signal, said A/D converter means providing a digital output signal, and, a digital integrating/auto-correlator means receiving said digital output signal from said A/D converter means, said digital integrating/auto-correlator means receiving an externally generated clock signal for synchronizing signal processing within itself, said digital integrating/auto correlator means generating a signal select control signal which is applied to said switching means to switch either of said first or second signal to the output of said switching means, said digital integrating/auto-correlator means also generating a sample control signal to establish the sampling period within said sample and hold means and a convert control signal to establish the A/D conversion period within said A/D converter means, said digital integrating/auto-correlator means digitally integrating and correlating said digital output signal to provide a digitally correlated output signal.

Claim 3

A digital integrating/auto-correlator apparatus as described in claim 1 wherein said digital intergrating/auto-correlator means comprises in combination: a timing means for receiving said clock signal, said timing means generating said signal select control signal, said sample control signal and said convert control signal, said timing means also generating an internal clock signal, an add/sub command signal and a clear signal, an arithmetic logic means for receiving the digital output signal from said A/D converter means, said arithmetic logic means including a four bit carry generator, said arithmetic logic means receiving said add/sub command signal from said timing means, said arithmetic logic means receiving a feedback signal, said arithmetic logic means processing said digital output signal and said feedback signal in response to said add/sub command signal, said arithmetic logic means providing a computation output, an accumulator means receiving said computation output, said accumulator means storing said computation output, said accumulator means providing said feedback signal to said arithmetic logic means, said accumulator means receiving said clock and said clear signal from said timing means, and an output latch means connected to said accumulator means to receive the output therefrom, said accumulator means having its output clocked into said output latch means upon the completion of a predetermined number of arithmetic operations by said arithmetic logic means, said accumulator means being cleared upon the transfer of its output to said output latch means, said output latch means receiving said clock signal from said timing means, said output latch means providing an auto-correlated output signal in response to said clock signal.

Claim 4

A digital integrating/auto-correlator apparatus as described in claim 2 wherein said arithmetic logic means has an integration period of 2 N+1 samples, where N is the number of bits of the particular A/D converter used.

Claim 5

A digital integrating/auto-correlator apparatus as described in claim 5 wherein said 2 N+1 samples comprise 2 N adds and 2 N subtracts.

Claim 6

A digital integrating/auto-correlator apparatus as described in claim 2 wherein said predetermined number of arithmetic operations equals 2 N+1 samples, where N is the number of bits of the particular A/D converter used.

Claim 7

A digital integrating/auto-correlator apparatus as described in claim 2 wherein said arithmetic logic means performs a 2 N bit parallel ADD or Subtract, where N is the number of bits of the particular A/D converter used.

Claim 8

A digital integrating/auto-correlator apparatus as described in claim 1 wherein said digital output signal comprises one group from the group of four bits, eight bits, ten bits, twelve bits, sixteen bits, or thirty two bits.

Claim 9

A digital integrating/auto-correlator apparatus as described in claim 1 wherein said digitally correlated output signal comprises one group from the group of four bits, eight bits, twelve bits, sixteen bits, or thirty two bits.