US4883990A
Expired / Lapsed
US
⏱️ 0.0 years remaining
ECL-TTL level converter
Assignee: NEC Corp
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Filing: 1988-10-31
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Granted: 1989-11-28
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Expires: 2008-10-31
Abstract
Abstract An ECL-TTL level converter having a three-state output level is disclosed. A circuit provided in the converter for forming the three-state output level includes a function for protecting IC's connected to the output terminal of the converter when an negative power voltage applied to the converter is an abnormal condition.
Inventors
- 👤 Yoshitaka Umeki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 09:45
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00307; H03K19/0175; H03K19/018; H03K19/01806; H03K19/01812; H03K19/02; H03K19/08; H03K19/082; H03K19/0823; H03K19/0826
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
357 words
A signal level converter comprising: a positive power supply line; a ground potential line; a negative power supply line; a first current switching logic circuit coupled to said ground potential line and to said negative power supply line, and having first, second and third ports; a second current switching logic circuit coupled to said ground potential line and to said negative power supply line, and having first, second and third ports; an input terminal connected to said first port of said first current switching logic circuit; a three-state control input terminal connected to said first port of said second current switching logic circuit; a reference potential terminal connected to said second ports of said first and second current switching logic circuits; a TTL circuit coupled to said positive power supply line and to said ground potential line, and including a phase-divide stage transistor, an output transistor and a off-buffer transistor, said phase-divide stage transistor having a base, a collector and an emitter; an output terminal connected to a connecting port between said output transistor and said off-buffer transistor; a first diode having an anode and a cathode, said anode being connected to said collector of said phase-divide stage transistor; a second diode having an anode and a cathode, said anode being connected to said base of said phase-divide stage transistor; a first transistor having a base, a collector and an emitter, said base being connected to said positive power supply line through a resistor, said emitter being connected to said ground potential line, and said collector being connected to said cathodes of said first and second diodes in common; a connecting means for connecting said third port of said first current switching logic circuit to said base of said phase-divide stage transistor to send a signal from said first current switching logic circuit to said phase-divide stage transistor; and a switching means connected to said base of said first transistor and to said third port of said second current switching logic circuit to render said first transistor in a conductive state or a nonconductive state in accordance with a signal from said second current switching logic circuit.
Claim 2
Dependent Claim
357 words
A signal level converter comprising: a positive power supply line; a ground potential line; a negative power supply line; a first current switching logic circuit coupled to said ground potential line and to said negative power supply line, and having first, second and third ports; a second current switching logic circuit coupled to said ground potential line and to said negative power supply line, and having first, second and third ports; an input terminal connected to said first port of said first current switching logic circuit; a three-state control input terminal connected to said first port of said second current switching logic circuit; a reference potential terminal connected to said second ports of said first and second current switching logic circuits; a TTL circuit coupled to said positive power supply line and to said ground potential line, and including a phase-divide stage transistor, an output transistor and a off-buffer transistor, said phase-divide stage transistor having a base, a collector and an emitter; an output terminal connected to a connecting port between said output transistor and said off-buffer transistor; a first diode having an anode and a cathode, said anode being connected to said collector of said phase-divide stage transistor; a second diode having an anode and a cathode, said anode being connected to said base of said phase-divide stage transistor; a first transistor having a base, a collector and an emitter, said base being connected to said positive power supply line through a resistor, said emitter being connected to said ground potential line, and said collector being connected to said cathodes of said first and second diodes in common; a connecting means for connecting said third port of said first current switching logic circuit to said base of said phase-divide stage transistor to send a signal from said first current switching logic circuit to said phase-divide stage transistor; and a switching means connected to said base of said first transistor and to said third port of said second current switching logic circuit to render said first transistor in a conductive state or a nonconductive state in accordance with a signal from said second current switching logic circuit.
Claim 3
Dependent Claim
74 words
A signal level converter of claim 1, in which said switching means is constituted by a second transistor having a base, a collector and an emitter, said base of said second transistor being connected to said ground potential line, said emitter of said second transistor being connected to said third port of said second current switching logic circuit and said collector of said second transistor being connected to said base of said first transistor.
Claim 4
Dependent Claim
81 words
A signal level converter of claim 2, in which said second current switching logic circuit includes an output transistor having a collector constituting said third port such that when said output transistor of said second current switching logic circuit is conductive, said second transistor is rendered conductive and said first transistor is rendered nonconductive, and when said output transistor of said second current switching logic circuit is nonconductive said second transistor is rendered nonconductive, and said first transistor is rendered conductive.
Claim 5
Dependent Claim
59 words
A signal level converter of claim 1, in which said switching means is constituted by a third diode having an anode and a cathode, said anode of said third diode being connected to said base of said first transistor, and said cathode of said third diode being connected to said third port of said second current switching logic circuit.
Claim 6
Dependent Claim
81 words
A signal level converter of claim 4, in which said second current switching logic circuit includes an output transistor having a collector constituting said third port such that when said output transistor of said second current switching logic circuit is conductive, said third diode is rendered conductive and said first transistor is rendered nonconductive, and when said output transistor of said second current switching logic circuit is nonconductive, said third diode is rendered nonconductive and said first transistor is rendered conductive.
Claim 7
Dependent Claim
58 words
A signal level converter of claim 4 further comprising a fourth diode having an anode and a cathode, said anode of said fourth diode being connected to said ground potential line and said cathode of said fourth diode being connected to said third port of said second current switching logic circuit with said cathode of said third diode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-27 | 1993-05-29 | 1993-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-27 | 1997-05-29 | 1997-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-27 | 2001-05-29 | 2001-11-28 | $7700.00 | Window Closed / Lapsed |