US4700087A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic signal level conversion circuit
Assignee: Maxim Integrated Products Inc
•
Filing: 1986-12-23
•
Granted: 1987-10-13
•
Expires: 2006-12-23
Abstract
Abstract A circuit for converting an input logic signal to an output logic signal having differing high and/or low logic voltage levels includes an output transistor and a load resistor coupling a collector of the output transistor to a supply voltage. The emitter of the output transistor is grounded. An input stage clamps a base of the output transistor to ground when the input signal voltage level is low, thereby turning the output transistor off and allowing the load resistor to pull the output signal, produced at the output transistor collector, up to its high logic level. When the input signal is high, the input stage unclamps the base of the output transistor from ground and a feedback stage responsive to the output signal supplies feedback current to the base of the output transistor, which feedback current increases with the magnitude of the output logic signal. The feedback current turns on the transistor, thereby increasing load current through the load resistor so as to reduce the output signal level. As the output signal level falls, the feedback stage reduces the feedback current such that the output signal reaches equilibrium at its low logic level and such that the output transistor is unsaturated.
Inventors
- 👤 Douglas J. Stroberger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:21
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/013; H03K19/0175; H03K19/018; H03K19/01806; H03K19/01812
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
208 words
A circuit for generating an output logic signal capable of assuming high and low logic levels, comprising: a source of common reference potential; a source of first supply voltage; a source of second supply voltage; a source of reference voltage; a load resistor; an output transistor having first and second load terminals for passing a load current therebetween and a control terminal, said first load terminal being connected to said load resistor such that said load current passes through said load resistor, said second load terminal being coupled to said common reference potential; a first transistor having a control terminal coupled to said reference voltage, having a first load terminal resistively coupled to said second supply voltage and coupled to the control terminal of said output transistor, and having a second load terminal resistively coupled to said first supply voltage; a second transistor having a control terminal coupled to the first load terminal of said output transistor, having a first load terminal coupled to said second supply voltage, and having a second load terminal coupled to the second load terminal of said first transistor; and means responsive to the input signal for alternatively clamping and unclamping the control terminal of said output transistor to said common reference potential.
Claim 2
Dependent Claim
208 words
A circuit for generating an output logic signal capable of assuming high and low logic levels, comprising: a source of common reference potential; a source of first supply voltage; a source of second supply voltage; a source of reference voltage; a load resistor; an output transistor having first and second load terminals for passing a load current therebetween and a control terminal, said first load terminal being connected to said load resistor such that said load current passes through said load resistor, said second load terminal being coupled to said common reference potential; a first transistor having a control terminal coupled to said reference voltage, having a first load terminal resistively coupled to said second supply voltage and coupled to the control terminal of said output transistor, and having a second load terminal resistively coupled to said first supply voltage; a second transistor having a control terminal coupled to the first load terminal of said output transistor, having a first load terminal coupled to said second supply voltage, and having a second load terminal coupled to the second load terminal of said first transistor; and means responsive to the input signal for alternatively clamping and unclamping the control terminal of said output transistor to said common reference potential.
Claim 3
Dependent Claim
47 words
The circuit according to claim 1 further comprising: a first resistor, coupling the control terminal of said second transistor being coupled to the first load terminal of said output transistor; and a second resistor, coupling the control terminal of said second transistor to said common reference potential.
Claim 4
Dependent Claim
189 words
A circuit for receiving an input logic signal capable of assuming first high and first low logic levels and for generating therefrom an output logic signal capable of assuming second high and second low logic levels, comprising: a source of common reference potential; a load resistor; an output transistor having a first and second load terminals for passing a load current therebetween and a control terminal, said first load terminal being connected to said load resistor such that said load current passes through said load resistor, said second load terminal being coupled to said common reference potential; a source of first reference voltage of magnitude less than said first high logic level and greater than said first low logic level; first means responsive to said input signal and said first reference voltage for clamping said control terminal of said output transistor to said common reference potential when the input signal voltage level is less than said first reference voltage; and second means for supplying a current to said control terminal of said output transistor of magnitude according to the potential of said first load terminal of said output transistor.
Claim 5
Dependent Claim
189 words
A circuit for receiving an input logic signal capable of assuming first high and first low logic levels and for generating therefrom an output logic signal capable of assuming second high and second low logic levels, comprising: a source of common reference potential; a load resistor; an output transistor having a first and second load terminals for passing a load current therebetween and a control terminal, said first load terminal being connected to said load resistor such that said load current passes through said load resistor, said second load terminal being coupled to said common reference potential; a source of first reference voltage of magnitude less than said first high logic level and greater than said first low logic level; first means responsive to said input signal and said first reference voltage for clamping said control terminal of said output transistor to said common reference potential when the input signal voltage level is less than said first reference voltage; and second means for supplying a current to said control terminal of said output transistor of magnitude according to the potential of said first load terminal of said output transistor.
Claim 6
Dependent Claim
118 words
The circuit according to claim 3 wherein said first means comprises: a source of first supply voltage; a first transistor having a control terminal for receiving said input signal, a first load terminal resistively coupled to said common reference potential, and a second load terminal resistively coupled to said first supply voltage; a first diode; a second transistor having a control terminal coupled to said first reference voltage, a first load terminal coupled to said common reference potential through said first diode, and a second load terminal coupled to the second load terminal of said first transistor; and a second diode coupling the first load terminal of said second transistor to the control terminal of said output transistor.
Claim 7
Dependent Claim
14 words
The circuit according to claim 3 wherein said second means comprises a differential amplifier.
Claim 8
Dependent Claim
118 words
The circuit according to claim 3 wherein said second means comprises: a source of second reference voltage; a source of second supply voltage; a third transistor having a control terminal coupled to said source of second reference potential, having a first load terminal resistively coupled to said second supply voltage and coupled to the control terminal of said output transistor, and having a second load terminal resistively coupled to said third supply voltage; and a fourth transistor having a control terminal coupled to the first load terminal of said output transistor, having a first load terminal coupled to said second supply voltage, and having a second load terminal coupled to the second load terminal of said third transistor.
Claim 9
Dependent Claim
331 words
A circuit for receiving an input logic signal capable of assuming first high and first low logic levels and for generating therefrom an output logic signal capable of assuming second high and second low logic levels, comprising: a source of common reference potential; a load resistor; an output transistor having first and second load terminals for passing a load current therebetween and a control terminal, said first load terminal being connected to said load resistor such that said load current passes through said load resistor, said second load terminal being coupled to said common reference potential; a source of first reference voltage of magnitude less than said first high logic level and greater than said first low logic level; a source of first supply voltage; a first transistor having a control terminal for receiving said input signal, a first load terminal coupled to said common reference potential, and a second load terminal resistively coupled to said first supply voltage; a first diode; a second transistor having a control terminal coupled to said first reference voltage, a first load terminal coupled to said common reference potential through said first diode, and a second load terminal coupled to the second load terminal of said first transistor; a second diode coupling the first load terminal of said second transistor to the control terminal of said output transistor; a source of second reference voltage; a source of second supply voltage; a third transistor having a control terminal coupled to said source of second reference potential, having a first load terminal resistively coupled to said second supply voltage and coupled to the control terminal of said output transistor, and having a second load terminal resistively coupled to said first supply voltage; and a fourth transistor having a control terminal coupled to the first load terminal of said output transistor, having a first load terminal coupled to said second supply voltage, and having a second load terminal coupled to the second load terminal of said third transistor.
Claim 10
Dependent Claim
331 words
A circuit for receiving an input logic signal capable of assuming first high and first low logic levels and for generating therefrom an output logic signal capable of assuming second high and second low logic levels, comprising: a source of common reference potential; a load resistor; an output transistor having first and second load terminals for passing a load current therebetween and a control terminal, said first load terminal being connected to said load resistor such that said load current passes through said load resistor, said second load terminal being coupled to said common reference potential; a source of first reference voltage of magnitude less than said first high logic level and greater than said first low logic level; a source of first supply voltage; a first transistor having a control terminal for receiving said input signal, a first load terminal coupled to said common reference potential, and a second load terminal resistively coupled to said first supply voltage; a first diode; a second transistor having a control terminal coupled to said first reference voltage, a first load terminal coupled to said common reference potential through said first diode, and a second load terminal coupled to the second load terminal of said first transistor; a second diode coupling the first load terminal of said second transistor to the control terminal of said output transistor; a source of second reference voltage; a source of second supply voltage; a third transistor having a control terminal coupled to said source of second reference potential, having a first load terminal resistively coupled to said second supply voltage and coupled to the control terminal of said output transistor, and having a second load terminal resistively coupled to said first supply voltage; and a fourth transistor having a control terminal coupled to the first load terminal of said output transistor, having a first load terminal coupled to said second supply voltage, and having a second load terminal coupled to the second load terminal of said third transistor.
References Cited (Backward Citations)
US3473047A
Cited
US3699355A
Cited
US3676713A
Cited
US3985954A
Cited
US4055794A
Cited
US4415817A
Cited
JPH115036A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-10-12 | 1991-04-13 | 1991-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-10-12 | 1995-04-13 | 1995-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-10-12 | 1999-04-13 | 1999-10-13 | $7700.00 | Window Closed / Lapsed |