US4883989A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for precharging a bus
Assignee: Sharp Corp
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Filing: 1988-08-29
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Granted: 1989-11-28
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Expires: 2008-08-29
Abstract
Abstract A circuit for precharging a bus has a first bus and a second bus separately and first and second driving MOS transistors respectively driving the first and second buses, and is so structured that a signal inputted to the first bus is transmitted to the gate of the second driving MOS transistor through a CMOS inverter to thereby drive the second bus and that a signal inputted to the second bus is transmitted to the gate of the first driving MOS transistor through another CMOS inverter to thereby drive the first bus. In this manner, a signal inputted to either of these buses causes these buses to be combined nonsynchronously.
Inventors
- 👤 Toshiaki Mizukami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 05:33
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
145 words
A circuit for precharging a bus comprising a first bus, a second bus, a first precharging MOS transistor precharging said first bus, a second precharging MOS transistor precharging said second bus, a first CMOS inverter, a second CMOS inverter, a first driving MOS transistor for driving said first bus, and a second driving MOS transistor for driving said second bus, said circuit being so structured that a signal inputted to said first bus is transmitted to the gate of said second driving MOS transistor through said second CMOS inverter to thereby drive said second bus and that a signal inputted to said second bus is transmitted to the gate of said first driving MOS transistor through said first CMOS inverter to thereby drive said first bus whereby a signal inputted to either of said buses causes said first and second buses to be combined non-synchronously.
Claim 2
Dependent Claim
145 words
A circuit for precharging a bus comprising a first bus, a second bus, a first precharging MOS transistor precharging said first bus, a second precharging MOS transistor precharging said second bus, a first CMOS inverter, a second CMOS inverter, a first driving MOS transistor for driving said first bus, and a second driving MOS transistor for driving said second bus, said circuit being so structured that a signal inputted to said first bus is transmitted to the gate of said second driving MOS transistor through said second CMOS inverter to thereby drive said second bus and that a signal inputted to said second bus is transmitted to the gate of said first driving MOS transistor through said first CMOS inverter to thereby drive said first bus whereby a signal inputted to either of said buses causes said first and second buses to be combined non-synchronously.
Claim 3
Dependent Claim
35 words
The circuit of claim 1 wherein said first and second driving MOS transistors are N-channel MOS transistors of which the sources are grounded and the drains are connected respectively to said first and second buses.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-27 | 1993-05-29 | 1993-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-27 | 1997-05-29 | 1997-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-27 | 2001-05-29 | 2001-11-28 | $7700.00 | Window Closed / Lapsed |