US4883985A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Mesfet latch circuit
Assignee: Panasonic Holdings Corp
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Filing: 1987-10-28
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Granted: 1989-11-28
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Expires: 2007-10-28
Abstract
Abstract An FET circuit suitable for a latch has a pair of inverters. The input stage FET of each of the inverters is connected such that the gate electrode thereof is connected to receive an output signal of the FET of the other inverter through a circuit having an FET and at least a diode. The sources of the input stage FETs are connected to a common connection point, and a current source arrangement such as a resistor is connected between the common connection point and a power supply terminal. The circuit provides an extended allowable range of the effective threshold voltage V T and has small power consumption.
Inventors
- 👤 Shin Katsu
- 👤 Shutaro Nambu
- 👤 Akio Shimano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:38
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/356034; H03K3/356043; H03K3/356052; H03K3/35606; H03K3/356069
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
217 words
An FET circuit comprising: a pair of inverters, each inverter comprising: an output terminal, resistive means, a first FET having drain, gate and source electrodes and having its drain electrode connected through said resistive means to a first power supply terminal, its gate electrode connected to said output terminal of the other said inverter and its source electrode connected to a first common connection point, and a second FET having drain, gate and source electrodes and having its drain electrode connected to the drain electrode of said first FET, its gate electrode connected to one of a set terminal and reset terminal and its source electrode connected to a second common connection point; said pair of inverters comprising a third FET having drain, gate and source electrodes and having its drain electrode connected to said first common connection point and its gate electrode connected to a reference voltage terminal, and a fourth FET having drain, gate and source electrodes and having its drain electrode connected to said second common connection point, its gate electrode connected to a clock terminal and its source electrode connected to the source electrode of the third FET at a third common connection point; and substantially constant current source means connected between said third common connection point and a second power supply terminal.
Claim 2
Dependent Claim
217 words
An FET circuit comprising: a pair of inverters, each inverter comprising: an output terminal, resistive means, a first FET having drain, gate and source electrodes and having its drain electrode connected through said resistive means to a first power supply terminal, its gate electrode connected to said output terminal of the other said inverter and its source electrode connected to a first common connection point, and a second FET having drain, gate and source electrodes and having its drain electrode connected to the drain electrode of said first FET, its gate electrode connected to one of a set terminal and reset terminal and its source electrode connected to a second common connection point; said pair of inverters comprising a third FET having drain, gate and source electrodes and having its drain electrode connected to said first common connection point and its gate electrode connected to a reference voltage terminal, and a fourth FET having drain, gate and source electrodes and having its drain electrode connected to said second common connection point, its gate electrode connected to a clock terminal and its source electrode connected to the source electrode of the third FET at a third common connection point; and substantially constant current source means connected between said third common connection point and a second power supply terminal.
Claim 3
Dependent Claim
20 words
An FET circuit in accordance with claim 1, wherein said second power supply terminal is connected to reference ground potential.
Claim 4
Dependent Claim
16 words
An FET circuit in accordance with claim 1, wherein said current source means is a resistor.
Claim 5
Dependent Claim
22 words
An FET circuit in accordance with claim 1, wherein said substantially constant current source means is a source-drain circuit of another FET.
Claim 6
Dependent Claim
22 words
An FET circuit in accordance with claim 4, wherein a gate electrode of said another FET is connected to its source electrode.
Claim 7
Dependent Claim
29 words
An FET circuit in accordance with claim 5, wherein said substantially constant current source means is a dual gate FET having two gate electrodes connected to its source electrode.
Claim 8
Dependent Claim
16 words
An FET circuit in accordance with claim 1, wherein said FETs are Schottky barrier gate FETs.
Claim 9
Dependent Claim
272 words
An FET circuit comprising: a pair of inverters, each inverter comprising: an output terminal, resistive means, a first FET having drain, gate and source electrodes and having its drain electrode connected through said resistive means to a first power supply terminal, its gate electrode connected to said output terminal of the other said inverter and its source electrode connected to a first common connection point, and a second FET having drain, gate and source electrodes and having its drain electrode connected to the drain electrode of said first FET, its gate electrode connected to one of a set terminal and reset terminal and its source electrode connected to a second common connection point; said pair of inverters comprising a third FET having drain, gate and source electrodes and having its drain electrode connected to said first common connection point and its gate electrode connected to a reference voltage terminal, and a fourth FET having drain, gate and source electrodes and having its drain electrode connected to said second common connection point, its gate electrode connected to a clock terminal and its source electrode connected to the source electrode of the third FET at a third common connection point; each said inverter further comprising diode means and a fifth FET having a gate electrode connected to the drain electrode of the first FET of the same inverter, a source electrode connected through said diode means to the output terminal of the same inverter and a drain electrode connected to said first power supply terminal; and substantially constant current source means connected between said third common connection point and a second power supply terminal.
Claim 10
Dependent Claim
272 words
An FET circuit comprising: a pair of inverters, each inverter comprising: an output terminal, resistive means, a first FET having drain, gate and source electrodes and having its drain electrode connected through said resistive means to a first power supply terminal, its gate electrode connected to said output terminal of the other said inverter and its source electrode connected to a first common connection point, and a second FET having drain, gate and source electrodes and having its drain electrode connected to the drain electrode of said first FET, its gate electrode connected to one of a set terminal and reset terminal and its source electrode connected to a second common connection point; said pair of inverters comprising a third FET having drain, gate and source electrodes and having its drain electrode connected to said first common connection point and its gate electrode connected to a reference voltage terminal, and a fourth FET having drain, gate and source electrodes and having its drain electrode connected to said second common connection point, its gate electrode connected to a clock terminal and its source electrode connected to the source electrode of the third FET at a third common connection point; each said inverter further comprising diode means and a fifth FET having a gate electrode connected to the drain electrode of the first FET of the same inverter, a source electrode connected through said diode means to the output terminal of the same inverter and a drain electrode connected to said first power supply terminal; and substantially constant current source means connected between said third common connection point and a second power supply terminal.
Claim 11
Dependent Claim
18 words
An FET circuit in accordance with claim 8, wherein said second FETs are of the normally ON type.
Claim 12
Dependent Claim
18 words
An FET circuit in accordance with claim 8, wherein said second and third power supply terminals are common.
Claim 13
Dependent Claim
18 words
An FET circuit in accordance with claim 10, wherein said second FETs are of the normally ON type.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-27 | 1993-05-29 | 1993-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-27 | 1997-05-29 | 1997-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-27 | 2001-05-29 | 2001-11-28 | $7700.00 | Window Closed / Lapsed |