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US4881199A
Expired / Lapsed
US
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Read circuit for reading the state of memory cells
Assignee: STMicroelectronics SA
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Filing: 1988-01-14
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Granted: 1989-11-14
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Expires: 2008-01-14
Abstract
Abstract A read circuit is disclosed for integrated circuits of the logic circuit type, comprising a memory consisting of a matrix of memory cells, the reading of which is done by the detection of a current variation or voltage variation, the memory cells being each addressable by rows and columns selected by row and column decoders, the read circuit being connected to memory cells by a line known as a bit line, and comprising a bit line pre-loading circuit and a detection circuit that detects the conduction or non-conduction of the addressed memory cell. The read circuit comprises a parallel-connected second identical detection circuit, the two detection circuits being connected to a common node of the bit line by means which provide for the simultaneous detection, at each read operation, of a "1" or a "0" regardless of the state of the memory cell addressed, and which provide for obtaining the data read at the output of at least one detection circuit. The invention can be applied to EPROMs in particular.
Inventors
- 👤 Jacek Kowalski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 07:44
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/22; G11C7/00; G11C7/24
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
309 words
A read circuit for an array of addressable memory cells, wherein said cells have two possible complementary logic states and the state of an addressed cell is readable by detecting a current variation on a bit line to which said cell is connected during a read operation, said read circuit comprising a first precharge circuit for precharging said bit line to a first specified voltage level prior to a read operation, and a first detection circuit having an input connected during a read operation, and a first detection circuit having an input connected during a read operation to said precharged bit line, for detecting a current variation on said bit line, said current variation depending on the state of the addressed cell, said read circuit further comprising: an isolation switch between said bit line and the input of said first detection circuit, said isolation switch rendered conductive only during a read operation; a second detection circuit identical to said first mentioned detection circuit and having an input connected to said bit line through at least a second isolation switch, said second switch also rendered conductive only during a read operation, a second precharge circuit connected to the input of said first mentioned detection circuit for precharging to a second specified voltage the input of said first detection circuit prior to a read operation, a third precharge circuit connected to the input of said second detection circuit, for precharging to a third specified voltage the input of said second detection circuit prior to a read operation; said specified voltages being such that whatever the state of the addressed cell, one of the two detection circuits will detect a current variation corresponding to the actual state of the addressed cell and the other detection circuit will detect a current variation corresponding to a state which is complementary of this actual state.
Claim 2
Dependent Claim
309 words
A read circuit for an array of addressable memory cells, wherein said cells have two possible complementary logic states and the state of an addressed cell is readable by detecting a current variation on a bit line to which said cell is connected during a read operation, said read circuit comprising a first precharge circuit for precharging said bit line to a first specified voltage level prior to a read operation, and a first detection circuit having an input connected during a read operation, and a first detection circuit having an input connected during a read operation to said precharged bit line, for detecting a current variation on said bit line, said current variation depending on the state of the addressed cell, said read circuit further comprising: an isolation switch between said bit line and the input of said first detection circuit, said isolation switch rendered conductive only during a read operation; a second detection circuit identical to said first mentioned detection circuit and having an input connected to said bit line through at least a second isolation switch, said second switch also rendered conductive only during a read operation, a second precharge circuit connected to the input of said first mentioned detection circuit for precharging to a second specified voltage the input of said first detection circuit prior to a read operation, a third precharge circuit connected to the input of said second detection circuit, for precharging to a third specified voltage the input of said second detection circuit prior to a read operation; said specified voltages being such that whatever the state of the addressed cell, one of the two detection circuits will detect a current variation corresponding to the actual state of the addressed cell and the other detection circuit will detect a current variation corresponding to a state which is complementary of this actual state.
Claim 3
Dependent Claim
39 words
A read circuit according to claim 1, wherein said second isolation switch is connected to the bit line through an inverter and said first, second, and third specified precharge voltages are equal to a common high logic level voltage.
Claim 4
Dependent Claim
17 words
A read circuit according to claim 2, wherein said first and second switch means are MOS transistors.
Claim 5
Dependent Claim
21 words
A read circuit according to claim 2, wherein said precharge circuits each comprises a MOS transistor connected to a supply voltage.
Claim 6
Dependent Claim
47 words
A read circuit according to claim 1, wherein said second isolation switch is directly connected to said bit line, said first and second specified precharge voltages are equal to a common high logic level voltage and said third specified voltage level is a low logic level voltage.
Claim 7
Dependent Claim
37 words
A read circuit according to claim 5, wherein said first and second precharge circuits each comprises a MOS transistor connected to a supply voltage, and said third precharge circuit comprises a transistor connected to a ground voltage.
Claim 8
Dependent Claim
25 words
A read circuit according to claim 6, wherein said first isolation switch comprises a NMOS transistor and said second isolation switch comprises a PMOS transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-13 | 1993-05-15 | 1993-11-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-13 | 1997-05-15 | 1997-11-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-13 | 2001-05-15 | 2001-11-14 | $7700.00 | Window Closed / Lapsed |