Patent US4879693A successfully refreshed from Google Patents.
US4879693A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Device for the self-synchronization of the output circuits of a memory using a three-state gate
Assignee: STMicroelectronics SA
•
Filing: 1987-12-03
•
Granted: 1989-11-07
•
Expires: 2007-12-03
Abstract
Abstract A self-synchronization device is disclosed for output circuits comprising a "3-state" gate of memories working in internal clock mode. This device consists of a sequential logic circuit which allows the "3-state" gate to go into low impedance only when a datum is available at the output of the read amplifiers.
Inventors
- 👤 Richard Ferrant
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:17
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057; G11C7/1006
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
74 words
A self-synchronization device for output circuits of memories working in an internal clock mode, comprising a "3-state" gate connected to the output of read amplifiers, the working of said memories being monitored by read and operation control signals W and E, said device comprising a sequential logic circuit which allows the "3-state" gate to go into low impedance only at the instant when a datum is available at the output of the read amplifiers.
Claim 2
Dependent Claim
74 words
A self-synchronization device for output circuits of memories working in an internal clock mode, comprising a "3-state" gate connected to the output of read amplifiers, the working of said memories being monitored by read and operation control signals W and E, said device comprising a sequential logic circuit which allows the "3-state" gate to go into low impedance only at the instant when a datum is available at the output of the read amplifiers.
Claim 3
Dependent Claim
59 words
Device according to the claim 1 wherein the sequential logic circuit consists of a D type latch flip-flop controlled by a pulsating clock signal, a reset signal and a signal at the terminal D, the said D type flip-flop emitting output Q and Q signals which control the "3-state" gate, the said sequential logic further comprising a storage loop.
Claim 4
Dependent Claim
23 words
Device according to the claim 2 wherein the read amplifier is controlled by the same pulsating clock signal as the D type flip-flop.
Claim 5
Dependent Claim
30 words
Device according to the claim 2 wherein the pulsating clock signal consists of pulses, the duration of which is at least equal to the response time of the read amplifier.
Claim 6
Dependent Claim
31 words
Device according to the claim 2 wherein the signal at the terminal D of the D type flip-flop is positioned at the logic level "1" at least during the read mode.
Claim 7
Dependent Claim
28 words
Device according to the claim 2 wherein the reset signal of the D type flip-flop comes from a combinational logic circuit controlled by the signals E and W.
Claim 8
Dependent Claim
42 words
Device according to the claim 6 wherein the combinational logic circuit comprises a NAND gate with one of its gates receiving the signal W and the other gate receiving the output of an inverter, the input of which receives the signal E.
Claim 9
Dependent Claim
68 words
Device according to the claim 2 wherein, when the memory comprises the control signal OE, the signals Q and Q of the D type flip-flop are sent respectively to an AND gate and to an OR gate before being sent to the "3-state" gate, the AND gate receiving the inverted signal OE at its other input and the OR gate receiving the signal OE at its other input.
Claim 10
Dependent Claim
21 words
Device according to the claim 2 wherein the storage loop consists of two transfer gates controlled by the clock signal 1.
References Cited (Backward Citations)
US4744063A
Cited
EP0144223A2
Cited
EP0180001A2
Cited
US4707810A
Cited
US4761767A
Cited
US4777623A
Cited
US4771405A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-06 | 1993-05-08 | 1993-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-06 | 1997-05-08 | 1997-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-06 | 2001-05-08 | 2001-11-07 | $7700.00 | Window Closed / Lapsed |