EP0144223A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1984-11-30
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Granted: —
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Expires: 2004-11-30
Abstract
Abstract A semiconductor memory device operated synchronously with clock signals, such as a MOS dynamic RAM device. The semiconductor memory device includes a switch circuit (7) inserted between a prestage output amplifier circuit (5a) receiving a readout signal (OUT') from a memory cell, and an output buffer circuit (6). The switch circuit is turned on just before the output signal (OUT') is supplied from the prestage output amplifier circuit to the output buffer circuit and turned off after the output condition (OUT) of the output buffer circuit is settled. The potential corresponding to the output data is maintained in the circuit between the switch circuit and the output buffer circuit. The output condition of the output buffer circuit is therefore retained even during the reset period of the prestage drive circuit, and the duration period of the output signal (OUT) is expanded.
Inventors
- 👤 Fumio Baba
- 👤 Hirohiko Mochizuki
- 👤 Hatsuo Miyahara
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 03:32
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4093; G11C7/1006
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
127 words
A semiconductor memory device comprising: a prestage output amplifier circuit receiving a readout signal from a memory cell; an output buffer circuit receiving the output signal of said prestage output amplifier circuit; and a switch circuit inserted between said prestage output amplifier circuit and said output buffer circuit; said switch circuit being turned on just before the output signal is supplied from said prestage output amplifier circuit to said output buffer circuit and turned off after the output condition of said output buffer circuit is settled; the potential corresponding to the output data being maintained in a circuit between said switch circuit and said output buffer circuit; thereby retaining the output condition of said output buffer circuit even during the reset period of said prestage drive circuit.
Claim 2
Dependent Claim
127 words
A semiconductor memory device comprising: a prestage output amplifier circuit receiving a readout signal from a memory cell; an output buffer circuit receiving the output signal of said prestage output amplifier circuit; and a switch circuit inserted between said prestage output amplifier circuit and said output buffer circuit; said switch circuit being turned on just before the output signal is supplied from said prestage output amplifier circuit to said output buffer circuit and turned off after the output condition of said output buffer circuit is settled; the potential corresponding to the output data being maintained in a circuit between said switch circuit and said output buffer circuit; thereby retaining the output condition of said output buffer circuit even during the reset period of said prestage drive circuit.
Claim 3
Dependent Claim
28 words
A semiconductor memory device according to claim 1, wherein said semiconductor memory device further comprises a switch drive circuit for supplying a drive signal to said switch circuit.
Claim 4
Dependent Claim
63 words
A semiconductor memory device according to claim 2, wherein said switch drive circuit comprises totempole connected MOS transistors driven by clock signals having opposite polarities and a bootstrap capacitor which is connected to the coupling point of said MOS transistors and which is driven by a clock signal so as to increase the amplitude of said drive signal supplied to said switch circuit.
Claim 5
Dependent Claim
58 words
A semiconductor memory device according to claim 1, 2, or 3, wheréin said semiconductor memory device further comprises a latch circuit which is inserted between said switch circuit and said output buffer circuit and which retains said output signal supplied from said prestage output amplifier circuit via said switch circuit even after said switch circuit is turned off.
Claim 6
Dependent Claim
46 words
A semiconductor memory device according to claim 4, wherein said latch circuit comprises a flip-flop circuit having a pair of driver transistors cross-coupled with each other at the gates and the drains and a pair of load means connected to the drains of said driver transistors.
Claim 7
Dependent Claim
87 words
A semiconductor memory device according to any preceding claim, wherein said prestage output amplifier circuit comprises a pair of driver transistors mutually cross-coupled at the gates and the drains, a pair of load transistors connected to the drains of said driver transistors, and a pair of input transistors inserted between the gates of said load transistors and data buses for receiving a readout signal from a selected memory cell, said prestage output amplifier being actuated by applying a clock signal to the drains of said load transistors.
Claim 8
Dependent Claim
43 words
A semiconductor memory device according to any preceding claim, wherein said output signal of said prestage output amplifier circuit includes a pair of complementary data signals and said switch circuit comprises a pair of MOS transistors switching said pair of complementary data signals.
References Cited (Backward Citations)
No citation records indexed.
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