US4761767A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High reliability integrated circuit memory
Assignee: Eurotechnique SA
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Filing: 1986-01-13
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Granted: 1988-08-02
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Expires: 2006-01-13
Abstract
Abstract The invention provides integrated circuit memories with repair circuits. These repair circuits allow redundant memory cell lines to be substituted for defective cell lines. The invention takes advantage of the existence of these substitution circuits for electrically, and no longer only functionally, decoupling the defective lines. A connection connects circuits for biasing the cell lines to the repair circuit of this line. When the line is repaired (i.e. neutralized) it is automatically unbiased.
Inventors
- 👤 Richard Ferrant
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 09:02
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/785; G11C29/83; G11C29/832
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
153 words
An integrated circuit memory, comprising: memory cells divided into lines and columns in a matrix, the cells of the same cell line being connected to the same connections called bit lines, said bit lines being each, on the one hand, biased by a power supply circuit and, on the other, each in series with a respective bit line selection circuit, repair circuits comprising means for disabling the selection circuit and thus placing bit lines of cell lines out of action and means for enabling circuits for selecting bit lines of additional cell lines which replace the cell lines placed out of action, and means for interrupting the power supply to the cell lines placed out of action wherein said power supply circuits each comprise a transistor connected to a supply terminal of a corresponding bit line of the memory, to a power supply terminal, and, by its control electrode, to said interrupting means.
Claim 2
Dependent Claim
153 words
An integrated circuit memory, comprising: memory cells divided into lines and columns in a matrix, the cells of the same cell line being connected to the same connections called bit lines, said bit lines being each, on the one hand, biased by a power supply circuit and, on the other, each in series with a respective bit line selection circuit, repair circuits comprising means for disabling the selection circuit and thus placing bit lines of cell lines out of action and means for enabling circuits for selecting bit lines of additional cell lines which replace the cell lines placed out of action, and means for interrupting the power supply to the cell lines placed out of action wherein said power supply circuits each comprise a transistor connected to a supply terminal of a corresponding bit line of the memory, to a power supply terminal, and, by its control electrode, to said interrupting means.
Claim 3
Dependent Claim
24 words
The memory as claimed in claim 1, wherein the interrupting means are controlled by the disabling and enabling means contained in the repair circuits.
Claim 4
Dependent Claim
37 words
The memory as claimed in any one of claim 1 or claim 2, wherein said selection circuits each comprise a transistor controlled by its control electrode at which it receives a selection order delivered by a decoder.
Claim 5
Dependent Claim
51 words
The memory as claimed in claim 1, wherein said interrupting means comprise a bistable circuit whose electric state is imposed by the condition, decomposed or not, of a fuse and a connection connecting the output of this bistable circuit to the control electrodes of the transistors of the power supply circuits.
Claim 6
Dependent Claim
75 words
The memory as claimed in claim 4, further comprising, for each cell line of the bit line selection circuits, one of said repair circuits, and a part of a decoder which concerns this cell line, the whole of these circuits being integrated in the memory, and the connection connecting the output of the repair circuit to the transistors of the biasing circuit extends in the memory parallel to the bit lines of the cell line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-02 | 1992-02-01 | 1992-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-02 | 1996-02-01 | 1996-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-02 | 2000-02-01 | 2000-08-02 | $7700.00 | Window Closed / Lapsed |