Patent US4866741A successfully refreshed from Google Patents.
US4866741A
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3/2 Frequency divider
Assignee: Seagate Technology LLC
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Filing: 1988-12-23
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Granted: 1989-09-12
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Expires: 2008-12-23
Abstract
Abstract A 3/2 frequency divider employs two D-type flip-flops, an OR gate and an AND gate arranged to respond to an input signal at a frequency f to derive an output signal at a frequency 2/3 f. The frequency divider is employed in a code converter to encode or decode 1, 7, 2, 3 codes.
Inventors
- 👤 Vadim B. Minuhin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 16:55
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1423; G11B20/1426
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
211 words
A 3/2 frequency divider responsive to an input signal having a frequency f to derive an output signal having a frequency 2/3f, comprising, in combination: a first D-type flip-flop having a D input, a clock input, a Q output and a Q-not output; a second D-type flip-flop having a D input, a clock input, a Q output and a Q-not output; input means for providing said input signal to the clock input of said first D-type flip-flop and for providing an inverse of said input signal to the clock input of said second D-type flip-flop; first logic means responsive to the Q-not outputs of said first and second D-type flip-flops for providing a signal of a first state to the D inputs of said first and second D-type flip-flops when the Q-not output of either of said D-type flip-flops is in said first state and for providing a signal of a second state to the D inputs of said first and second D-type flip-flops when the Q-not outputs of both of said first and second D-type flip-flops are in said second state, said first state being opposite said second state; and second logic means responsive to the Q outputs of said first and second D-type flip-flops to provide said output signal.
Claim 2
Dependent Claim
211 words
A 3/2 frequency divider responsive to an input signal having a frequency f to derive an output signal having a frequency 2/3f, comprising, in combination: a first D-type flip-flop having a D input, a clock input, a Q output and a Q-not output; a second D-type flip-flop having a D input, a clock input, a Q output and a Q-not output; input means for providing said input signal to the clock input of said first D-type flip-flop and for providing an inverse of said input signal to the clock input of said second D-type flip-flop; first logic means responsive to the Q-not outputs of said first and second D-type flip-flops for providing a signal of a first state to the D inputs of said first and second D-type flip-flops when the Q-not output of either of said D-type flip-flops is in said first state and for providing a signal of a second state to the D inputs of said first and second D-type flip-flops when the Q-not outputs of both of said first and second D-type flip-flops are in said second state, said first state being opposite said second state; and second logic means responsive to the Q outputs of said first and second D-type flip-flops to provide said output signal.
Claim 3
Dependent Claim
23 words
Apparatus according to claim 1 wherein said first logic means is on OR gate and said second logic means is an AND gate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-11 | 1993-03-13 | 1993-09-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-11 | 1997-03-13 | 1997-09-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-11 | 2001-03-13 | 2001-09-12 | $7700.00 | Window Closed / Lapsed |