Digital data processing apparatus with pipelined memory cycles

Claim 1

In a digital data processing apparatus utilizing a common bus structure for transferring information between functional units including a processing unit, a peripheral control unit, and first and second memory units, at least the first said memory unit including dynamic storage elements, said apparatus including clock means connected with said functional units for providing signals defining successive timing intervals, said apparatus executing a unit-to-unit information transfer on the bus structure by transferring signals representative of a transfer cycle that occurs during plural timing intervals and includes plural phases, including a definition phase which includes addressing, a response phase, and a data-transfer phase, where the phases of one cycle are non-overlapping and occur in sequence in different respective timing intervals of the transfer cycle, said bus structure including means for carrying definition signals representative of definition phases and data signals representative of data-transfer phases, said functional units pipelining transfer cycles by transferring concurrently on the bus structure signals representative of differing phases of plural cycles, the improvement comprising A. signalling means for periodically generating a JIFFY signal indicative a necessity to refresh at least one said dynamic storage element, B. memory refresh means connected with said first memory unit for normally responding to said JIFFY signal for executing a memory refresh cycle, said refresh cycle refreshing at least one dynamic storage element in said first memory unit, said memory refresh means including means for generating a BUSY signal indicative of onset of said memory refresh cycle, C. said memory refresh means comprises memory update means for responding to said KIFFY signal and to a signal indicating that the second memory unit requires a memory update from the first memory unit for executing a memory update cycle to transfer stored information from said first memory unit to said second memory unit, said memory update means including means for initiating said update cycle during a first timing interval common to first and second pipelined transfer cycles, said memory update means further including means generating a BUSY signal indicative of the onset of said update cycle, and D. pipeline-interrupt means responsive to detection of said BUSY signal for aborting further execution of said first transfer cycle while continuing execution of said second transfer cycle.