US4279034A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital communication system fault isolation circuit
Assignee: AT&T Inc
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Filing: 1979-11-15
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Granted: 1981-07-14
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Expires: 1999-11-15
Abstract
Abstract There is disclosed, for use in a digital communication system, a fault detector circuit operable for removing faulty stations from the system. The disclosed circuit uses a distributed bypass isolation technique and may be used with individual stations or with groups of stations. A multi-bit delay register is connected across each station or station group and the output of the delay register is compared with the output of the parallel stations. When differences in the compared bits are detected the parallel stations are immediately isolated from the system and the bits from the delay register are placed in the system to preserve synchronism. This arrangement has the advantage of allowing immediate corrective action to occur to protect the sanity of the system. In situations where the system is divided into a voice digital bus and a data digital bus different error techniques may be employed for each bus.
Inventors
- 👤 Leslie A. Baxter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 04:17
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/28; H04L12/42; H04L12/437; H04B; H04B1/00; H04B1/74; H04B1/745
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
148 words
A fault isolation circuit for use in a digital loop communication system having a plurality of stations, each station interconnected with a next preceding and a next succeeding station over a digital communication path, said stations separated into groups, each group containing at least one said station, said isolation circuit including delay means having a bit propagation delay time equal to the bit propagation time of the combination of said associated group of stations, means for propagating through said delay means data bits appearing at the input of said associated group of stations, means for comparing the output bits from said group of stations with said propagated delayed bits, and error detector means responsive to a detected error between said compared bits for isolating said output bits from said communication path and for substituting said propagated delayed bits on said communication path in place of said isolated bits.
Claim 2
Dependent Claim
148 words
A fault isolation circuit for use in a digital loop communication system having a plurality of stations, each station interconnected with a next preceding and a next succeeding station over a digital communication path, said stations separated into groups, each group containing at least one said station, said isolation circuit including delay means having a bit propagation delay time equal to the bit propagation time of the combination of said associated group of stations, means for propagating through said delay means data bits appearing at the input of said associated group of stations, means for comparing the output bits from said group of stations with said propagated delayed bits, and error detector means responsive to a detected error between said compared bits for isolating said output bits from said communication path and for substituting said propagated delayed bits on said communication path in place of said isolated bits.
Claim 3
Dependent Claim
46 words
The invention set forth in claim 1 wherein said error detector means includes means for counting the bit changes between the input and output of said associated group of stations, and means for comparing said bit changes against a preset acceptable number of said bit changes.
Claim 4
Dependent Claim
37 words
The invention set forth in claim 1 wherein said digital loop includes a plurality of individual communication paths interconnecting said stations and wherein said error detecting means is arranged to independently monitor the bits on each path.
Claim 5
Dependent Claim
138 words
The invention set forth in claim 3 further comprising a plurality of delay means each individually associated with each said path each means having a delay time equal to the bit delay propagation time of the combination of said associated stations, means for propagating through each said delay means data bits appearing on a particular one of said communication paths at the input of said associated group of stations, means for comparing the output bits on each communication path from said group of stations with said bits propagated through said associated delay means, and means responsive to a detected error between said compared bits on a particular one of said communication paths for isolating said output bits from said particular communication path and for substituting on said particular communication path said bits propagated through said associated delay means.
Claim 6
Dependent Claim
128 words
A communication system having a plurality of stations interconnected together in sequential fashion, said stations arranged into groups with each group containing at least one said station, said communication system including an isolation circuit associated with at least one of said station groups, said isolation circuit including means for comparing communication signal input to said associated station group with communication signal output from said associated station group, an auxiliary communication path arranged to process said input signals and to maintain synchronism between said input communication signals and said output communication signals, error detection means for detecting error between said compared communication signals, means responsive to a detected error for inhibiting said communication signal output and for substituting therefor communication signals from the output of said auxiliary communication path.
Claim 7
Dependent Claim
128 words
A communication system having a plurality of stations interconnected together in sequential fashion, said stations arranged into groups with each group containing at least one said station, said communication system including an isolation circuit associated with at least one of said station groups, said isolation circuit including means for comparing communication signal input to said associated station group with communication signal output from said associated station group, an auxiliary communication path arranged to process said input signals and to maintain synchronism between said input communication signals and said output communication signals, error detection means for detecting error between said compared communication signals, means responsive to a detected error for inhibiting said communication signal output and for substituting therefor communication signals from the output of said auxiliary communication path.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-07-13 | 1985-01-12 | 1985-07-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-07-13 | 1989-01-12 | 1989-07-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-07-13 | 1993-01-12 | 1993-07-14 | $7700.00 | Window Closed / Lapsed |