Patent US3303708A successfully refreshed from Google Patents.
Patent US3362862A successfully refreshed from Google Patents.
Patent US1234847A successfully refreshed from Google Patents.
Patent US4860260A successfully refreshed from Google Patents.
US4860260A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device with testing of redundant memory cells
Assignee: Toshiba Corp
•
Filing: 1987-06-09
•
Granted: 1989-08-22
•
Expires: 2007-06-09
Abstract
Abstract A semiconductor memory device includes a main memory cell array, a redundancy memory cell array, bonding pads for receiving an address signal, a row decoder for selecting a row of the main memory cell array in accordance with the row address signal, and an exchange controller connected to receive the address signal, which is programmable to inhibit the selective operation of the row decoder to select the row of the redundancy memory cell array, in response to specific address signals. The semiconductor memory device further includes bonding pads, each for receiving a test signal. The exchange controller is connected to receive the test signal for inhibiting the selective operation of the row decoder and selecting the row of the redundancy memory cell array, in response to the test signal.
Inventors
- 👤 Shinji Saito
- 👤 Shigeru Atsumi
- 👤 Sumio Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:49
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/781; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/24
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
115 words
A semiconductor memory device capable of operation in a test mode and an operation mode, comprising: a memory unit including a plurality of main memory blocks and at least one redundancy memory block; selection means for programmably selecting one of said main memory blocks or said at least one redundancy memory block, said selection means being programmable to select one of said at least one redundancy memory block in place of a specified main memory block when said device is in said operation mode; and control means for disabling said selection means in said test mode and for selecting said one redundancy memory block for testing when said selection means has not yet been programmed.
Claim 2
Dependent Claim
115 words
A semiconductor memory device capable of operation in a test mode and an operation mode, comprising: a memory unit including a plurality of main memory blocks and at least one redundancy memory block; selection means for programmably selecting one of said main memory blocks or said at least one redundancy memory block, said selection means being programmable to select one of said at least one redundancy memory block in place of a specified main memory block when said device is in said operation mode; and control means for disabling said selection means in said test mode and for selecting said one redundancy memory block for testing when said selection means has not yet been programmed.
Claim 3
Dependent Claim
41 words
A semiconductor memory device according to claim 1, wherein said at least one redundancy memory block includes a single redundancy memory block, and said control means includes a bonding pad for receiving a test signal supplied to set the test mode.
Claim 4
Dependent Claim
54 words
A semiconductor memory device according to claim 2, wherein said control means includes: a control circuit, connected to said bonding pad, for disabling said selection means in response to the test signal; and a selection circuit connected to said bonding pad for selecting the single redundancy memory block in response to the test signal.
Claim 5
Dependent Claim
36 words
A semiconductor memory device according to claim 3, wherein said control means includes a potential setting means for causing said bonding pad to be set at a predetermined potential in the absence of said test signal.
Claim 6
Dependent Claim
27 words
A semiconductor memory device according to claim 4, wherein said potential setting means includes a resistive means connected between said bonding pad and a preset potential terminal.
Claim 7
Dependent Claim
52 words
A semiconductor memory device according to claim 1, wherein said at least one redundancy memory block includes a plurality of redundancy memory blocks, and wherein said control means includes a plurality of bonding pads, each of said bonding pads being capable of receiving a test signal supplied to set the test mode.
Claim 8
Dependent Claim
70 words
A semiconductor memory device according to claim 6, wherein said control means includes: a control circuit connected to each of said bonding pads for disabling said selection means in response to the test signal; and a plurality of selection circuits connected to the respective bonding pads, each of said selection circuits including means for selecting different one of said plurality of redundancy memory blocks in response to the test signal.
Claim 9
Dependent Claim
45 words
A semiconductor memory device according to claim 7, wherein said control means includes a plurality of potential setting circuits, each of said circuits including means for causing a corresponding bonding pad to be set at a predetermined potential in the absence of said test signal.
Claim 10
Dependent Claim
30 words
A semiconductor memory device according to claim 8, wherein each of said potential setting circuits includes a resistance means connected between the corresponding bonding pad and a preset potential terminal.
Claim 11
Dependent Claim
173 words
A semiconductor memory device according to claim 1, wherein said at least one redundancy memory block includes a plurality of redundancy memory blocks, and wherein said control means includes: a first bonding pad for receiving a test signal supplied to cause such device to operate in the test mode; a plurality of second bonding pads for receiving a test address signal supplied to designate one of the plurality of redundancy memory blocks; a decoding circuit having a plurality of output terminals for decoding said test address signal in response to said test signal to generate an internal test signal at one of the plurality of output terminals; a control circuit connected to each of the output terminals of said decoding circuit for disabling said selection means in response to the internal test signal; and a plurality of selection circuits connected to the respective output terminals of said decoding circuit, each of said selection circuits including means for selecting a different one of said redundancy memory blocks in response to the internal test signal.
Claim 12
Dependent Claim
133 words
A semiconductor memory device according to claim 10, wherein said first bonding pad serves as an input terminal for an operation signal having a first and second voltage level, and said test signal having a voltage level different than said first and second voltage levels, and wherein the device includes means for setting the potential of said first bonding pad at one of said first and second voltage levels in response to the operation signal and at said voltage level different than said first and second voltage levels in response to the test signal, and wherein said decoding circuit is connected to said first bonding pad by a test signal detector designed to detect that the first bonding pad is set at the voltage level different than said first and second voltage levels.
Claim 13
Dependent Claim
43 words
A semiconductor memory device according to claim 10, wherein said second bonding pads serve as input terminals for receiving an address signal supplied to designate one of said main memory blocks in the absence of said test signal at said first bonding pad.
Claim 14
Dependent Claim
16 words
A semiconductor memory device according to claim 1, wherein said semiconductor memory device is an EPROM.
Claim 15
Dependent Claim
36 words
A semiconductor memory device according to claim 1, wherein said memory unit is a matrix array of memory cells arranged in rows and columns, and each memory block includes the memory cells of the same row.
References Cited (Backward Citations)
JPS56297A
Cited
US4392211A
Cited
US4365319A
Cited
US4428068A
Cited
US4468759A
Cited
US4651304A
Cited
US4648075A
Cited
US4549101A
Cited
US4720818A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-21 | 1993-02-20 | 1993-08-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-21 | 1997-02-20 | 1997-08-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-21 | 2001-02-20 | 2001-08-22 | $7700.00 | Window Closed / Lapsed |