Patent US4859624A successfully refreshed from Google Patents.
US4859624A
Expired / Lapsed
US
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Manufacturing method of semiconductor device having CCD and peripheral circuit
Assignee: Toshiba Corp
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Filing: 1988-07-29
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Granted: 1989-08-22
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Expires: 2008-07-29
Abstract
Abstract In a method of manufacturing a semiconductor device which has a CCD and its peripheral circuit on the same substrate, a buried channel for a CCD and an impurity diffusion region for peripheral circuit transistors are formed at the same time by a single process, the impurity diffusion region being of the same conductivity type as that of the buried channel.
Inventors
- 👤 Hiroshige Goto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 18:36
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
88 words
A method of manufacturing a semiconductor device comprising the steps of: forming a buried channel for a CCD in a semiconductor substrate; and forming an impurity diffusion region in which a transistor for a peripheral circuit of the CCD having a conductivity type opposite to that of the buried channel is formed, the impurity diffusion region being of the same conductivity type as that of the buried channel; and wherein said buried channel and said impurity diffusion region being formed at the same time by a single process.
Claim 2
Independent Claim
88 words
A method of manufacturing a semiconductor device comprising the steps of: forming a buried channel for a CCD in a semiconductor substrate; and forming an impurity diffusion region in which a transistor for a peripheral circuit of the CCD having a conductivity type opposite to that of the buried channel is formed, the impurity diffusion region being of the same conductivity type as that of the buried channel; and wherein said buried channel and said impurity diffusion region being formed at the same time by a single process.
Claim 3
Dependent Claim
25 words
The method of manufacturing a semiconductor device according to claim 1, wherein said buried channel and said impurity diffusion region are formed through ion implantation.
Claim 4
Dependent Claim
36 words
The method of manufacturing a semiconductor device according to claim 1, wherein said substrate, said buried channel and said impurity diffusion region of the same conductivity as that of said buried channel are all of n-type.
Claim 5
Dependent Claim
34 words
The method of manufacturing a semiconductor device according to claim 3, further comprising the steps of forming a p-well for CCD in said substrate, and forming an n-type buried channel in said p-type well.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-21 | 1993-02-20 | 1993-08-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-21 | 1997-02-20 | 1997-08-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-21 | 2001-02-20 | 2001-08-22 | $7700.00 | Window Closed / Lapsed |