US4642877A — Method for making charge coupled device (CCD)-com…

Claim 1

Independent Claim 275 words

A CTD/CMOS process comprising the steps of: (a) providing an epitaxial layer of a first type semiconductor material; (b) providing a tank of an opposite type semiconductor material in said epitaxial layer of first type semiconductor material for selected transistors of complementary (CMOS); (c) patterning a moat masking layer over the epitaxial layer; (d) ion implanting a selected type material through the moat for forming channel separations between N and P channel transistors, and isolation regions and channel stops for the charge transfer devices (CTDs); (e) growing an oxide layer over the epitaxial layer; (f) providing a first poly layer of a semiconductor material; (g) growing an oxide layer on the poly layer; (h) depositing a nitride layer on the oxide layer; (i) patterning the nitride layer and selectively etching the poly layer for a stacked capacitor; (j) patterning the nitride layer and ion implanting selected type material for both N-channel and P-channel threshold adjust; (k) ion implanting selected type material for forming buried channels for the CTDs; (l) providing CTD clock wells by ion implanting selected type material in the CTD regions; (m) providing a second level layer of poly semiconductor material selectively to complete the stacked capacitors and transistor gates CTD clock gates; (n) providing source and drain regions by ion implanting selected type materials for source and drain regions into the CMOS regions for completing the CMOS circuitry; (o) providing virtual phase regions in the CTD regions by ion implanting selected type material for deepening the potential profile of the virtual phase region, barrier and well for completing the CTD circuitry; and (p) providing electrical contacts for the CMOS and CTD circuitry.

Claim 2

Dependent Claim 275 words

A CTD/CMOS process comprising the steps of: (a) providing an epitaxial layer of a first type semiconductor material; (b) providing a tank of an opposite type semiconductor material in said epitaxial layer of first type semiconductor material for selected transistors of complementary (CMOS); (c) patterning a moat masking layer over the epitaxial layer; (d) ion implanting a selected type material through the moat for forming channel separations between N and P channel transistors, and isolation regions and channel stops for the charge transfer devices (CTDs); (e) growing an oxide layer over the epitaxial layer; (f) providing a first poly layer of a semiconductor material; (g) growing an oxide layer on the poly layer; (h) depositing a nitride layer on the oxide layer; (i) patterning the nitride layer and selectively etching the poly layer for a stacked capacitor; (j) patterning the nitride layer and ion implanting selected type material for both N-channel and P-channel threshold adjust; (k) ion implanting selected type material for forming buried channels for the CTDs; (l) providing CTD clock wells by ion implanting selected type material in the CTD regions; (m) providing a second level layer of poly semiconductor material selectively to complete the stacked capacitors and transistor gates CTD clock gates; (n) providing source and drain regions by ion implanting selected type materials for source and drain regions into the CMOS regions for completing the CMOS circuitry; (o) providing virtual phase regions in the CTD regions by ion implanting selected type material for deepening the potential profile of the virtual phase region, barrier and well for completing the CTD circuitry; and (p) providing electrical contacts for the CMOS and CTD circuitry.

Claim 3

Dependent Claim 350 words

A CCD/CMOS process for producing a signal processing apparatus comprising the steps of: (a) providing a silicon epitaxial layer; (b) providing an N-tank region for a P-channel MOSFET in said epitaxial layer; (c) growing SiO 2 layer on the epitaxial layer and depositing a Si 3 N 4 layer on the SiO 2 layer; (d) patterning a moat over the epitaxial layer; (e) selectively masking the moat, etching the Si 3 N 4 layer and providing a CCD pattern and ion implanting P-type material for forming channel separations between N and P channel transistors and for forming isolation regions and channel stops for the CCDs; (f) after cleanup including removal of the Si 3 N 4 layer and at least 2000 Angstroms of the SiO 2 , growing a layer of SiO 2 on the epitaxial layer; (g) providing a first poly silicon layer on the SiO 2 layer and an N-type ion implant made onto the SiO 2 layer; (h) growing a SiO 2 layer on the poly silicon layer and depositing a Si 3 N 4 layer on the SiO 2 layer; (i) patterning the Si 3 N 4 layer and etching the poly layer for a stacked capacitor; (j) patterning the Si 3 N 4 layer and and ion implanting P-type material for both N-channel and P-channel threshold adjust; (k) after patterning, ion implanting an N-type material for forming buried channels for the CCDs; (l) providing CCD clock wells by ion implanting N-type material in the CCD regions: (m) providing a second level layer of poly silicon material selectively to complete the stacked capacitors, transistor gates and CCD clock gates; (n) providing source and drain regions by ion implanting N+ material P+ material, respectively, to form N+ source and drain regions and P+ source and drain regions for completing the CMOS circuitry; (o) providing virtual phase regions in the CCD regions by ion implanting N type material and for deepening the potential profile of the virtual phase region, barrier and well for completing the CCD circuitry; and (p) providing electrical contacts for the CMOS and CCD circuitry.

Claim 4

Dependent Claim 350 words

A CCD/CMOS process for producing a signal processing apparatus comprising the steps of: (a) providing a silicon epitaxial layer; (b) providing an N-tank region for a P-channel MOSFET in said epitaxial layer; (c) growing SiO 2 layer on the epitaxial layer and depositing a Si 3 N 4 layer on the SiO 2 layer; (d) patterning a moat over the epitaxial layer; (e) selectively masking the moat, etching the Si 3 N 4 layer and providing a CCD pattern and ion implanting P-type material for forming channel separations between N and P channel transistors and for forming isolation regions and channel stops for the CCDs; (f) after cleanup including removal of the Si 3 N 4 layer and at least 2000 Angstroms of the SiO 2 , growing a layer of SiO 2 on the epitaxial layer; (g) providing a first poly silicon layer on the SiO 2 layer and an N-type ion implant made onto the SiO 2 layer; (h) growing a SiO 2 layer on the poly silicon layer and depositing a Si 3 N 4 layer on the SiO 2 layer; (i) patterning the Si 3 N 4 layer and etching the poly layer for a stacked capacitor; (j) patterning the Si 3 N 4 layer and and ion implanting P-type material for both N-channel and P-channel threshold adjust; (k) after patterning, ion implanting an N-type material for forming buried channels for the CCDs; (l) providing CCD clock wells by ion implanting N-type material in the CCD regions: (m) providing a second level layer of poly silicon material selectively to complete the stacked capacitors, transistor gates and CCD clock gates; (n) providing source and drain regions by ion implanting N+ material P+ material, respectively, to form N+ source and drain regions and P+ source and drain regions for completing the CMOS circuitry; (o) providing virtual phase regions in the CCD regions by ion implanting N type material and for deepening the potential profile of the virtual phase region, barrier and well for completing the CCD circuitry; and (p) providing electrical contacts for the CMOS and CCD circuitry.

Claim 5

Dependent Claim 31 words

The CCD/CMOS process according to claim 2 wherein the silicon epitaxial layer includes a P+ silicon substrate and a 14-16 micron thick epitaxial P-type silicon layer formed on the silicon substrate.

Claim 6

Dependent Claim 27 words

The CCD/CMOS process according to claim 3 wherein at least 800 Angstroms of SiO 2 is grown on the epitaxial layer and has a 9-11 Ohm/cm resistivity.

Claim 7

Dependent Claim 24 words

The CCD/CMOS process according to claim 4 wherein at least 1400 Angstroms of Si 3 N 4 is deposited on the SiO 2 layer.

Claim 8

Dependent Claim 51 words

The CCD/CMOS process according to claim 5 wherein the Si 3 N 4 layer is patterned and etched away together with the corresponding portion of the SiO 2 layer and phosphorus ion implanted at a concentration of at least 5.5×10 12 /cm 3 and 80 KeV to form the N-tank region.

Claim 9

Dependent Claim 40 words

The CCD/CMOS process according to claim 6 wherein the layer of SiO 2 includes a region at least 5300 Angstroms thick grown over the N-tank region with the remaining Si 3 N 4 layer and corresponding SiO 2 etched away.

Claim 10

Dependent Claim 51 words

The CCD/CMOS process according to claim 2 wherein the SiO 2 layer further includes at least a 1100 Angstrom SiO 2 layer grown over the epitaxial layer including the silicon dioxide grown over the N-tank region and the Si 3 N 4 layer deposited thereon is at least 1400 Angstroms thick.

Claim 11

Dependent Claim 58 words

The CCD/CMOS process according to claim 2 wherein the P-type material for channel separation between N and P channel transistors is boron implanted at 5.5×10 12 /cm 3 and 90 KeV and the P+ type material for the P+ isolation regions and channel stops for the CCD is boron implanted at 1.0×10 14 /cm 3 and 60 KeV.

Claim 12

Dependent Claim 30 words

The CCD/CMOS process according to claim 2 wherein the SiO 2 layer for the poly silicon layer and the poly silicon layer are, respectively, 550-650 Angstroms and 4800-5200 Angstroms thick.

Claim 13

Dependent Claim 44 words

The CCD/CMOS process according to claim 2 wherein the SiO 2 layer grown over the poly silicon is 175-225 Angstroms thick and the Si 3 N 4 layer deposited on the SiO 2 layer is at least 200 Angstroms thick for the stacked capacitor.

Claim 14

Dependent Claim 28 words

The CCD/CMOS process according to claim 2 wherein the P-type material for both N-channel and P-channel threshold adjust is boron ion implanted at 4×10 11 and 40 KeV.

Claim 15

Dependent Claim 31 words

The CCD/CMOS process according to claim 2 wherein the N-type material for forming the buried channels for the CCDs is phosphorus ion implanted at 3.8×10 12 /cm 3 and 100 KeV.

Claim 16

Dependent Claim 28 words

The CCD/CMOS process according to claim 2 wherein the N-type material for the CCD clock wells is arsenic ion implanted at 1.8×10 12 /cm 3 and 40 KeV.

Claim 17

Dependent Claim 53 words

The CCD/CMOS process according to claim 2 wherein the second level layer of poly silicon is provided by growing at least 600 Angstroms SiO 2 , depositing at least 5000 Angstrom poly silicon on the SiO 2 and etching the poly silicon to form the stacked capacitors, transistor gates and CCD clock gates.

Claim 18

Dependent Claim 46 words

The CCD/CMOS process according to claim 2 wherein the N+ source and drain regions material is phosphorus ion implanted at 5×10 15 and 130 KeV, and the P+ source and drain regions material is BF 2 ion implanted at 4×10 15 /cm 3 and 130 KeV.

Claim 19

Dependent Claim 28 words

The CCD/CMOS process according to claim 2 wherein the N type material for the virtual well is phosphorus ion implanted at 4.2×10 12 /cm 3 and 100 KeV.

Claim 20

Dependent Claim 47 words

The CCD/CMOS process according to claim 2 wherein the N-type material ion implanted in the CCD regions for deepening the potential profile of the virtual phase region, barrier and well for completing the CCD circuitry is phosphorus ion implanted at 7.2×10 12 /cm 3 and 105 KeV.

Claim 21

Dependent Claim 21 words

The CCD/CMOS process according to claim 2 wherein the electrical contacts for the CMOS and CCD circuitry are formed using aluminum.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1990-02-16	1990-08-18	1991-02-17	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1994-02-16	1994-08-18	1995-02-17	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1998-02-16	1998-08-18	1999-02-17	$7700.00	Window Closed / Lapsed

Method for making charge coupled device (CCD)-complementary metal oxide semiconductor (CMOS) devices

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