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US4858182A
Expired / Lapsed
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High speed zero power reset circuit for CMOS memory cells
Assignee: Texas Instruments Inc
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Filing: 1986-12-19
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Granted: 1989-08-15
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Expires: 2006-12-19
Abstract
Abstract A reset circuit for a CMOS memory array is disclosed wherein the voltage supply for the standard six transistor memory cell is replaced by a pair of parallel connected transistors disposed between a fixed voltage source and the memory cell. The transistors are controlled by the reset signal and are complementary in that one is n-channel and the other is p-channel. The n-channel transistor is sized to prevent excess current flow to the memory cells to prevent an excessive charge build up therein for a logical "1" representation. In addition, the n-channel transistor provides a Vtn drop thereacross to prevent current flow in the memory cells during reset.
Inventors
- 👤 Roland H. Pang
- 👤 Edison H. Chiu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:26
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/20
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
104 words
A reset circuit for a memory array having at least one memory cell comprising: (a) a source of reset signals; (b) a source of supply voltage Vcc applied to said memory cells; and (c) first and second parallel-connected transistors coupled between said supply voltage source and each said memory cell in said memory array, said first transistor turned off and said second transistor turned on in the presence of said reset signals, said second transistor shifting said supply voltage downward to Vcc2 in the presence of said reset signals providing a current limited zero power condition in said cells of said array during reset.
Claim 2
Dependent Claim
104 words
A reset circuit for a memory array having at least one memory cell comprising: (a) a source of reset signals; (b) a source of supply voltage Vcc applied to said memory cells; and (c) first and second parallel-connected transistors coupled between said supply voltage source and each said memory cell in said memory array, said first transistor turned off and said second transistor turned on in the presence of said reset signals, said second transistor shifting said supply voltage downward to Vcc2 in the presence of said reset signals providing a current limited zero power condition in said cells of said array during reset.
Claim 3
Dependent Claim
18 words
A reset circuit as set forth in claim 1 wherein said memory cell is a CMOS memory cell.
Claim 4
Dependent Claim
25 words
A reset circuit as set forth in claim 1 wherein said first transistor is a p-channel transistor and said second transistor is an n-channel transistor.
Claim 5
Dependent Claim
25 words
a reset circuit as set forth in claim 1 wherein said first transistor has a minimal threshold voltage drop thereacross relative to said second transistor.
Claim 6
Dependent Claim
22 words
A reset circuit as set forth in claim 1 wherein said second transistor is sized to provide a predetermined maximum current flow.
Claim 7
Dependent Claim
120 words
A reset circuit for a CMOS memory array comprising: (a) a source of reset signals; (b) a source of supply voltage applied to said CMOS memory array; (c) a first transistor coupled between said source of supply voltage and said memory array, said first transistor having a minimal threshold voltage drop thereacross when a low voltage signal is applied to an input of said first transistor; and (d) a second transistor parallel-connected to said first transistor and coupled between said source of supply voltage and said memory array, said second transistor shifting the source of supply voltage to a lower level applied to said CMOS memory array when said reset signal is applied to an input of said second transistor.
Claim 8
Dependent Claim
120 words
A reset circuit for a CMOS memory array comprising: (a) a source of reset signals; (b) a source of supply voltage applied to said CMOS memory array; (c) a first transistor coupled between said source of supply voltage and said memory array, said first transistor having a minimal threshold voltage drop thereacross when a low voltage signal is applied to an input of said first transistor; and (d) a second transistor parallel-connected to said first transistor and coupled between said source of supply voltage and said memory array, said second transistor shifting the source of supply voltage to a lower level applied to said CMOS memory array when said reset signal is applied to an input of said second transistor.
Claim 9
Dependent Claim
14 words
The reset circuit of claim 6 wherein said first transistor is a p-channel transistor.
Claim 10
Dependent Claim
14 words
The reset circuit of claim 6 wherein said second transistor is an n-channel transistor.
Claim 11
Dependent Claim
19 words
The reset circuit of claim 6 wherein said second transistor is sized to provide a predetermined maximum current flow.
References Cited (Backward Citations)
US3757313A
Cited
US4489404A
Cited
US4567578A
Cited
US4418401A
Cited
EP0189700A2
Cited
JPS64686A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-14 | 1993-02-13 | 1993-08-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-14 | 1997-02-13 | 1997-08-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-14 | 2001-02-13 | 2001-08-15 | $7700.00 | Window Closed / Lapsed |