US4418401A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Latent image ram cell
Assignee: International Business Machines Corp
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Filing: 1982-12-29
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Granted: 1983-11-29
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Expires: 2002-12-29
Abstract
Abstract An asymmetric RAM cell is disclosed which will have a predictable initial storage state when pulsed drain voltage is turned on and yet after the initial turn-on interval, will operate in a symmetric fashion storing either binary ones or zeros. Thus, an initial prestored set of information can be permanently provided in a memory array made up of such cells, by orienting each individual cell at the time of manufacture so as to selectively represent either a binary one or zero. This is illustrated in the FIGURE where the upper cell has a first state by virtue of its orientation and the lower cell has a second, opposite state by virtue of its relative opposite orientation. When the array is turned on, the upper cell will have the opposite binary state from the lower cell. Thereafter, each cell can be respectively switched for storing ones and zeros in a normal RAM operating mode.
Inventors
- 👤 Jai P. Bansal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:52
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/20
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
179 words
A latent image storage cell, comprising: an N channel depletion mode load FET device having its drain/source path connected between a pulsed drain voltage and a first node, having its gate connected to said first node; a first N channel enhancement mode FET device having its drain/source path connected between said first node and ground potential, and its gate connected to a second node; a P channel enhancement mode FET device having its drain/source path connected between said pulsed drain voltage and said second node, and its gate connected to said first node; a second N channel enhancement mode FET device having its source/drain path connected between said second node and said ground potential, and having its gate connected to said first node; said first node charging up faster than said second node when said pulsed drain voltage turns on, providing a latent image operation for the circuit, the circuit operating as a RAM circuit by selectively applying positive or ground potential to said first or said second node to dynamically store a selected binary state in the circuit.
Claim 2
Dependent Claim
179 words
A latent image storage cell, comprising: an N channel depletion mode load FET device having its drain/source path connected between a pulsed drain voltage and a first node, having its gate connected to said first node; a first N channel enhancement mode FET device having its drain/source path connected between said first node and ground potential, and its gate connected to a second node; a P channel enhancement mode FET device having its drain/source path connected between said pulsed drain voltage and said second node, and its gate connected to said first node; a second N channel enhancement mode FET device having its source/drain path connected between said second node and said ground potential, and having its gate connected to said first node; said first node charging up faster than said second node when said pulsed drain voltage turns on, providing a latent image operation for the circuit, the circuit operating as a RAM circuit by selectively applying positive or ground potential to said first or said second node to dynamically store a selected binary state in the circuit.
Claim 3
Dependent Claim
525 words
A latent image read only memory and read/write memory circuit including a first and a second bit line and a plurality of storage cells, each said storage cell being switchably connected to said first and second bit lines by a word line signal on a corresponding one of a plurality of word lines, the circuit comprising: a first latent image storage cell in said circuit, comprising: a first N channel depletion mode load FET device having its drain/source path connected between a pulsed drain voltage and a first node, having its gate connected to said first node, said first node being switchably connected by means of a first word line signal to said first bit line; a first N channel enhancement mode FET device having its drain/source path connected between said first node and ground potential, and its gate connected to a second node, said second node being switchably connected by means of said first word line signal to said second bit line; a first P channel enhancement mode FET device having its drain/source path connected between said pulsed drain voltage and said second node, and its gate connected to said first node; a second N channel enhancement mode channel FET device having its drain/source path connected between said second node and said ground potential, and having its gate connected to said first node; said first node charging up faster than said second node when said pulsed drain voltage turns on, providing a first binary state latent image operation for said first cell, said first cell operating as a read/write memory by selectively applying positive or ground potential to said first or said second node to dynamically store a selected binary state in said first cell; a second latent image storage cell in said circuit, comprising: a second N channel depletion mode load FET device having its drain/source path connected between said pulsed drain voltage and a third node, having its gate connected to said third node, said third node being switchably connected by means of a second word line signal to said second bit line; a third N channel enhancement mode FET device having its drain/source path connected between said third node and ground potential, and its gate connected to a fourth node, said fourth node being switchably connected by means of said second word line signal to said first bit line; a second P channel enhancement mode FET device having its drain/source path connected between said pulsed drain voltage and said fourth node, and its gate connected to said third node; a fourth N channel enhancement mode FET device having its drain/source path connected between said fourth node and said ground potential, and having its gate connected to said third node; said third node charging up faster than said fourth node when said pulsed drain voltage turns on, providing a second binary state latent image operation for said second cell opposite from said first binary state for said first cell, said second cell operating as a read/write memory by selectively applying positive or ground potential to said third or said fourth node to dynamically store a selected binary state in said second cell.
Claim 4
Dependent Claim
525 words
A latent image read only memory and read/write memory circuit including a first and a second bit line and a plurality of storage cells, each said storage cell being switchably connected to said first and second bit lines by a word line signal on a corresponding one of a plurality of word lines, the circuit comprising: a first latent image storage cell in said circuit, comprising: a first N channel depletion mode load FET device having its drain/source path connected between a pulsed drain voltage and a first node, having its gate connected to said first node, said first node being switchably connected by means of a first word line signal to said first bit line; a first N channel enhancement mode FET device having its drain/source path connected between said first node and ground potential, and its gate connected to a second node, said second node being switchably connected by means of said first word line signal to said second bit line; a first P channel enhancement mode FET device having its drain/source path connected between said pulsed drain voltage and said second node, and its gate connected to said first node; a second N channel enhancement mode channel FET device having its drain/source path connected between said second node and said ground potential, and having its gate connected to said first node; said first node charging up faster than said second node when said pulsed drain voltage turns on, providing a first binary state latent image operation for said first cell, said first cell operating as a read/write memory by selectively applying positive or ground potential to said first or said second node to dynamically store a selected binary state in said first cell; a second latent image storage cell in said circuit, comprising: a second N channel depletion mode load FET device having its drain/source path connected between said pulsed drain voltage and a third node, having its gate connected to said third node, said third node being switchably connected by means of a second word line signal to said second bit line; a third N channel enhancement mode FET device having its drain/source path connected between said third node and ground potential, and its gate connected to a fourth node, said fourth node being switchably connected by means of said second word line signal to said first bit line; a second P channel enhancement mode FET device having its drain/source path connected between said pulsed drain voltage and said fourth node, and its gate connected to said third node; a fourth N channel enhancement mode FET device having its drain/source path connected between said fourth node and said ground potential, and having its gate connected to said third node; said third node charging up faster than said fourth node when said pulsed drain voltage turns on, providing a second binary state latent image operation for said second cell opposite from said first binary state for said first cell, said second cell operating as a read/write memory by selectively applying positive or ground potential to said third or said fourth node to dynamically store a selected binary state in said second cell.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-11-28 | 1987-05-30 | 1987-11-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-11-28 | 1991-05-30 | 1991-11-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-11-28 | 1995-05-30 | 1995-11-29 | $7700.00 | Window Closed / Lapsed |