Static RAM having a flash clear function

Claim 1

An integrated circuit static RAM having an array of memory cells each of which comprises a flip-flop having first and second nodes, each of which first and second nodes is connected: to a first power supply terminal through pull up means; to one of a pair of bit lines through a pass transistor having a gate controlled by a word line; to a second power supply terminal through one of a pair of data storage transistors and current return means to ground; and to a gate of the other of said pair of data storage transistors; and said RAM further includes reset means, connected to a selected one of said first and second nodes of at least one of said memory cells, for forcing said selected node to a predetermined voltage state, whereby said at least one of said memory cells may be set simultaneously to a logical state represented by said predetermined voltage state; characterized in that: said reset means is connected to said selected one of said first and second nodes through a corresponding data storage transistor, and said RAM further comprises a controllable clearing circuit for establishing a connection state to a terminal of one of said pair of data storage transistors that is either a normal state of a low - impedance path to ground or a clearing state of current path to a predetermined non-zero voltage source; said RAM further comprises controlling means responsive to a predetermined signal for switching said controllable clearing circuit from said normal state to said clearing state, whereby all those of said array of memory cells connected to said controllable clearing circuit may be forced simultaneously into a data state determined by said predetermined non-zero voltage.