Liquid cooled high density packaging for high speed circuits

Claim 1

A liquid cooled high density packaging system for high speed integrated circuit chips, comprising: a. a housing means having removable and hermetically sealed closure means, and which contains printed circuit substrate means; b. a plurality of integrated circuit chip means each having a bottom surface being directly bonded to a respective sintered stainless steel pad at a top surface thereof; c. said plurality of integrated circuit chip means with sintered stainless steel pads in turn being mounted onto said printed circuit substrate means and directly electrically interconnected into circuitry of said printed circuit substrate means to form an electronic assembly; d. said integrated circuit chip means with sintered stainless steel pads being mounted to said printed circuit substrate means in a manner which allows for movement due to differential in coefficient of expansion between said integrated circuit chip means, said housing means, and said printed circuit substrate means; e. said housing being filled with a dielectric fluid coolant which submerges said electronic assembly and thereby completely surrounds the said integrated circuit chip means and sintered stainless steel pads with said fluid coolant; f. said sintered stainless pads providing solid mounts for said integrated circuit chip means and also acting as wicks to draw said fluid coolant to one surface of said integrated circuit chip means while the opposite surface thereof is in direct contact with said fluid coolant, thus enabling said fluid coolant to boil due to heat generated by the said integrated chip means and remove great amounts of said generated heat as a result of liquid to vapor transformation of the fluid coolant and thereby limit the temperature of said integrated circuit chip means to the boiling point of said fluid coolant, whereby higher integrated circuit chip means density on the printed circuit substrate means is achievable due to lower output capacitance and the permissible use of shorter interconnections between chips as well as elimination of chip carriers.