Semiconductor memory cell including cross-coupled bipolar transistors and Schottky diodes

Claim 2

A solid state memory, comprising: a plurality of memory cells for holding digital data, said cells being comprised of a pair of cross coupled bipolar transistors with each of said transistors having a base, and wherein said cells are arranged in rows and columns; conductive access lines to said cells, wherein four of said access lines are connected to each of said cells and said digital data in each of said cells can be altered, without affecting the digital logic state in the remaining of said cells, by the application of electrical signals to said bases of said transistors; current sources for supplying current to said cells to store said digital data, wherein each of said current sources supplies current to more than one of said cells; and a plurality of Schottky diodes, wherein said electrical signals are applied to said bases of said transistors within each said cells through a unique pair of said Schottky diodes.

Claim 3

An electrical circuit, comprising: means for selectively switching the flow of electrical current between one of two conductive paths, said current switching means including a first terminal for controlling the flow of said current through a second terminal, and a third terminal for controlling the flow of said current through a fourth terminal; first and second unidirectional current conducting means wherein said unidirectional current conducting means are Schottky diodes; and first, second third and fourth current conducting access lines over which digital logic signals can flow, wherein said first access line is directly electrically connected to said first unidirectional current conducting means, said second access line is directly electrically connected to said second unidirectional current conducting means, said third access line is directly electrically connected to said second terminal, said fourth access line is directly electrically connected to said fourth terminal and none of said access lines are directly electrically connected to any other of said access lines.

Claim 4

An electrical circuit, comprising: means for selectively switching the flow of electrical current between one of two conductive paths, said current switching means including a first terminal for controlling the flow of said current through a second terminal, and a third terminal for controlling the flow of said current through a fourth terminal; first and second unidirectional current conducting means wherein said unidirectional current conducting means are Schottky diodes; and first, second third and fourth current conducting access lines over which digital logic signals can flow, wherein said first access line is directly electrically connected to said first unidirectional current conducting means, said second access line is directly electrically connected to said second unidirectional current conducting means, said third access line is directly electrically connected to said second terminal, said fourth access line is directly electrically connected to said fourth terminal and none of said access lines are directly electrically connected to any other of said access lines.

Claim 5

The circuit of claim 2 wherein electrical energy for said current switching means is supplied only through said access lines.

Claim 6

The circuit of claim 2 wherein said current switching means is a bistable, regenerative electrical circuit.

Claim 7

The circuit of claim 4 wherein said bistable regenerative electrical circuit includes: a first bipolar semiconductor transistor having a first base, first emitter and a first collector, wherein said first base is said first terminal; and a second bipolar semiconductor transistor having a second base, a second emitter and a second collector, wherein said second base is said third terminal, said first base is directly electrically connected to said second collector and said second base is directly electrically connected to said first collector.

Claim 8

The circuit of claim 5 wherein said first and second bipolar semiconductor transistors are adapted to operate in the normal or forward current mode.

Claim 9

An electrical circuit, comprising: a first electrical device having first, second and third regions wherein said first region is adapted to control the flow of current between said second and third regions; a second electrical device having fourth, fifth and sixth regions, wherein said fourth region is adapted to control the flow of current between said fifth and sixth regions, said first region is directly electrically connected to said sixth region and said third region is directly electrically connected to said fourth region; a third electrical device having seventh, eighth and ninth regions wherein said seventh region is adapted to control the flow of current between said eighth and ninth regions; a fourth electrical device having tenth, eleventh and twelfth regions wherein said tenth region is adapted to control the flow of current between said eleventh and twelfth region, said seventh region is directly electrically connected to said twelfth region and said ninth region is directly electrically connected to said tenth region; first, second, third and fourth unidirectional current conducting means, said unidirectional current conducting means being Schottky diodes and being directly electrically connected, respectively, to said first, second, third and fourth regions; and first, second, third, fourth, fifth and sixth current conducting access lines, wherein said first, second, third and fourth access lines are directly electrically connected, respectively, to said first, second, third and fourth unidirectional current conducting means, said fifth access line is directly electrically connected to said second region and said eighth region, and said sixth access line is directly electrically connected to said fifth region and said eleventh region.

Claim 10

An electrical circuit, comprising: a first electrical device having first, second and third regions wherein said first region is adapted to control the flow of current between said second and third regions; a second electrical device having fourth, fifth and sixth regions, wherein said fourth region is adapted to control the flow of current between said fifth and sixth regions, said first region is directly electrically connected to said sixth region and said third region is directly electrically connected to said fourth region; a third electrical device having seventh, eighth and ninth regions wherein said seventh region is adapted to control the flow of current between said eighth and ninth regions; a fourth electrical device having tenth, eleventh and twelfth regions wherein said tenth region is adapted to control the flow of current between said eleventh and twelfth region, said seventh region is directly electrically connected to said twelfth region and said ninth region is directly electrically connected to said tenth region; first, second, third and fourth unidirectional current conducting means, said unidirectional current conducting means being Schottky diodes and being directly electrically connected, respectively, to said first, second, third and fourth regions; and first, second, third, fourth, fifth and sixth current conducting access lines, wherein said first, second, third and fourth access lines are directly electrically connected, respectively, to said first, second, third and fourth unidirectional current conducting means, said fifth access line is directly electrically connected to said second region and said eighth region, and said sixth access line is directly electrically connected to said fifth region and said eleventh region.

Claim 11

The circuit of claim 7 wherein electrical energy is supplied to said first, second, third and fourth electrical devices only through said access lines.

Claim 12

The circuit of claim 7 wherein said first, second, third and fourth electrical devices are bipolar semiconductor transistors.

Claim 13

The circuit of claim 9 wherein said bipolar semiconductor transistors are each adapted to operate in the normal or forward current mode.

Claim 14

A digital memory circuit, comprising: means for selectively switching the flow of electrical current between one of two conductive paths, said current switching means including a first terminal for controlling the flow of said current through a second terminal, and a third terminal for controlling the flow of said current through a fourth terminal; first and second unidirectional current conducting means, wherein said unidirectional current conducting means are Schottky diodes; first, second, third and fourth current conducting access lines over which digital logic signals can flow, wherein said first access line is directly electrically connected to said first unidirectional current conducting means, said second access line is directly electrically connected to said second unidirectional current conducting means, said third access line is directly electrically connected to said second terminal and said fourth access line is directly electrically connected to said fourth terminal; and an electrical current source, wherein said electrical current source supplies current to said current switching means only through said access lines.

Claim 15

A digital memory circuit, comprising: means for selectively switching the flow of electrical current between one of two conductive paths, said current switching means including a first terminal for controlling the flow of said current through a second terminal, and a third terminal for controlling the flow of said current through a fourth terminal; first and second unidirectional current conducting means, wherein said unidirectional current conducting means are Schottky diodes; first, second, third and fourth current conducting access lines over which digital logic signals can flow, wherein said first access line is directly electrically connected to said first unidirectional current conducting means, said second access line is directly electrically connected to said second unidirectional current conducting means, said third access line is directly electrically connected to said second terminal and said fourth access line is directly electrically connected to said fourth terminal; and an electrical current source, wherein said electrical current source supplies current to said current switching means only through said access lines.

Claim 16

The circuit of claim 11 wherein said current switching means is a bistable, regenerative elecrical circuit.

Claim 17

The circuit of claim 12 wherein said bistable regenerative electrical circuit includes: a first bipolar semiconductor transistor having a first base, first emitter and a first collector, wherein said first base is said first terminal; and a second bipolar semiconductor transistor having a second base, second emitter and a second collector, wherein said second base is said third terminal, said first base is directly electrically connected to said second collector and said second base is directly electrically connected to said first collector.

Claim 18

The circuit of claim 13 wherein said first and second bipolar semiconductor transistors are adapted to operate in the forward or normal current mode.