Hybrid storage circuit

Claim 2

A low power dissipating memory cell comprising: a pair of field effect storage transistors, each having two current conducting terminals and a gate terminal, a first one of said current conducting terminals of each field effect storage transistor being connected to the gate terminal of the other field effect storage transistor to form a bistable storage circuit; a pair of bipolar load transistors, each having an emitter, collector and base terminal, the emitter-collector path of each of said bipolar load transistors being serially connected to said first one of said current conducting terminals of each of said pair of field effect storage transistors; a pair of bit lines, each bit line connected to the second current conducting terminal of one of said field effect storage transistors; and a word line commonly connected to both of said bipolar load transistors.

Claim 3

The memory cell of claim 1 further including: means for applying a common reference potential to the base terminals of said bipolar load transistors, and wherein said word line is connected to the emitter terminals of said bipolar load transistors.

Claim 4

The memory cell of claim 2 wherein said bipolar and field effect tRansistors are complementary transistor types.

Claim 5

The memory cell of claim 3 wherein said bipolar load transistors are PNP type transistors.

Claim 6

The memory cell of claim 2 further including: means for applying a low standby current to said word line when said cell is in an unselected state; and potential supply means for maintaining said bit lines at a fixed potential during said unselected state.

Claim 7

The memory cell of claim 5 further including: means for applying a select current to said word line when said cell is in a selected state, said select current being higher than said standby current; and means for sensing the presence of a current difference in said bit lines representative of the state of said memory cell during said selected state.

Claim 8

The memory cell of claim 6 further including: write means for selectively changing the potential of at least one of said bit lines during said selected state to cause said cell to assume one of two bistable conditions.

Claim 9

The memory cell of claim 7 wherein the capacitive voltage nodes at the first one of said current conducting terminals of said field effect storage transistors has sufficient capacity to fix the gate potential of the field effect storage transistor to be turned off during writing for the duration of the switching time of said field effect storage transistor to be turned off.

Claim 10

The memory cell of claim 2 including: means for changing said common reference potential applied to the base terminals of said bipolar load transistors during said selected state.

Claim 11

A low standby power dissipating memory array comprising: a plurality of memory cells arranged to form a matrix of rows and columns, each cell comprising a pair of cross-coupled field effect transistors, one current conducting electrode of each field effect transistor being connected to the gate electrode of the other form a bistable circuit, each of said cells further including a pair of bipolar load transistors associated with each field effect transistor, and having its collector connected to said one current conducting electrode; a plurality of word lines, each word line commonly connected to the emitters of each of said bipolar load transistors in each memory cell in the same row; a plurality of first bit lines, each first bit line commonly connected to the other of the current conducting electrodes of one of said field effect transistors in each cell in the same column; a plurality of second bit lines, each second bit line commonly connected to the other current conducting electrode of the other field effect transistor in each cell in the same column; reference potential means for applying a reference potential to the base of each bipolar load transistor; and control signal means for selectively providing control signals to said word and bit lines to provide reading, writing and sensing of at least one of said memory cells.

Claim 12

A low standby power dissipating memory array comprising: a plurality of memory cells arranged to form a matrix of rows and columns, each cell comprising a pair of cross-coupled field effect transistors, one current conducting electrode of each field effect transistor being connected to the gate electrode of the other form a bistable circuit, each of said cells further including a pair of bipolar load transistors associated with each field effect transistor, and having its collector connected to said one current conducting electrode; a plurality of word lines, each word line commonly connected to the emitters of each of said bipolar load transistors in each memory cell in the same row; a plurality of first bit lines, each first bit line commonly connected to the other of the current conducting electrodes of one of said field effect transistors in each cell in the same column; a plurality of second bit lines, each second bit line commonly connected to the other current conducting electrode of the other field effect transistor in each cell in the same column; reference potential means for applying a reference potential to the base of each bipolar load transistor; and control signal means for selectively providing control signals to said word and bit lines to provide reading, writing and sensing of at least one of said memory cells.

Claim 13

The memory array of claim 10 wherein said control signal means comprises means for applying a low standby current to said word lines during an unselected state and for selectively providing a higher select current to at least one of said word lines during a selected state.

Claim 14

The memory array of claim 11 further including: means for sustaining said bit lines at a fixed potential during said unselected state.

Claim 15

An integrated semiconductor structure comprising: a substrate of one type conductivity; an isolation region of opposite type conductivity extending from one surface of said substrate; first regions of said one type conductivity extending from said one surface of said substrate and enclosed within said isolation region to form the drain regions of a first and second storage field effect transistor; second regions of said one type conductivity extending from said one surface of said substrate and enclosed within said isolation region to form the source regions of said first and second storage fielD effect transistors; first regions of opposite type conductivity extending from said one surface of said substrate outside of said isolation region to form the emitter region of a first and second bipolar load transistor; second regions of said opposite type conductivity extending from said one surface of said substrate outside of said isolation region to form the collector regions of said first and second bipolar load transistors; first conductive means forming a gate electrode for said first storage field effect transistor and for interconnecting the drain region of said second storage field effect transistor and the collector region of one of said bipolar load transistors; second conductive means forming a gate electrode for said second storage field effect transistor and for interconnecting the drain region of said first storage field effect transistor and the collector region of the other of said bipolar load transistors; and means for applying signals to the source regions of said storage field effect transistors, said substrate and said emitter region to enable said structure to operate as a storage cell.

Claim 16

An integrated semiconductor structure comprising: a substrate of one type conductivity; an isolation region of opposite type conductivity extending from one surface of said substrate; first regions of said one type conductivity extending from said one surface of said substrate and enclosed within said isolation region to form the drain regions of a first and second storage field effect transistor; second regions of said one type conductivity extending from said one surface of said substrate and enclosed within said isolation region to form the source regions of said first and second storage fielD effect transistors; first regions of opposite type conductivity extending from said one surface of said substrate outside of said isolation region to form the emitter region of a first and second bipolar load transistor; second regions of said opposite type conductivity extending from said one surface of said substrate outside of said isolation region to form the collector regions of said first and second bipolar load transistors; first conductive means forming a gate electrode for said first storage field effect transistor and for interconnecting the drain region of said second storage field effect transistor and the collector region of one of said bipolar load transistors; second conductive means forming a gate electrode for said second storage field effect transistor and for interconnecting the drain region of said first storage field effect transistor and the collector region of the other of said bipolar load transistors; and means for applying signals to the source regions of said storage field effect transistors, said substrate and said emitter region to enable said structure to operate as a storage cell.

Claim 17

The integrated semiconductor structure of claim 13 wherein: said first regions of said one type conductivity extend laterally and are common to a plurality of substantially identical storage cell.

Claim 18

The integrated semiconductor structure of claim 14 wherein said regions of opposite type conductivity are formed simultaneously.

Claim 19

The integrated semiconductor structure of claim 13 wherein said substrate is N-type conductivity.