EP0095411A2
Expired / Lapsed
EP
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Bipolar memory cell
Assignee: Fairchild Semiconductor Corp
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Filing: 1983-05-17
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Granted: —
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Expires: 2003-05-17
Abstract
Abstract A bipolar memory cell is fabricated by forming diodes 60 and 65 on top of the transistors Q1 and Q2 formed in the underlying substrate 10. Metal silicide 30 overlies strips 34 and 35 of doped polycrystalline silicon 25, 28, 37, and 38 to cross-couple the bases and collectors of the two transistors 01 and 02 forming the memory cell. The metal silicide 30 shorts PN junctions 29 in polycrystalline 23. Two further strips 50 and 52, each comprising a sandwich of P type polycrystalline silicon 42, metal silicide 45, and N conductivity type polycrystalline silicon 47, are formed to couple the cross-coupled bases and collectors to respective diodes 60 and 65. The diodes 60 and 65 are formed by depositing metal 62 and 64 in electrical contact with the underlying N type polycrystalline silicon 47.
Inventors
- 👤 Madhukar B. Vora
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 07:42
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10B; H10B10/00; H10B10/10; Y; Y10; Y10S; Y10S257/00; Y10S257/914; Y10S257/926
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
206 words
An integrated circuit memory cell comprising: a semi conductor substrate (10); a first transistor (12, 17, 58) and a second transistor (12, 18) formed in the semiconductor substrate, each including a base, a collector, and an emitter; first (38, 37) and second (28, 25) connections of semiconductor material each extending between the base (17, 18) of one of the first and second transistors and the collector of the other of the first and second transistors, portions of the first (38, 37) and second (28, 25) connections being doped to correspond to the conductivity type of the base of the collector contacted; first (30b) and second (30a) regions of electrically conductive material deposited on the first (38, 37) and second (28, 25) connections, respectively, to short any PN junctions therein; third (42b, 45b, 47b and fourth (42a, 45a, 47a) regions, each including at least a layer of semiconductor material deposited on the substrate, to contact the base of the first and second transistors, respectively; and fifth (62) and sixth (64) regions of electrically conductive material deposited in contact with selected portions of the third ans fourth regions, respectively, to thereby form first and second Schottky diodes connected to the bases of the first and second transistors, respectively.
Claim 2
Dependent Claim
206 words
An integrated circuit memory cell comprising: a semi conductor substrate (10); a first transistor (12, 17, 58) and a second transistor (12, 18) formed in the semiconductor substrate, each including a base, a collector, and an emitter; first (38, 37) and second (28, 25) connections of semiconductor material each extending between the base (17, 18) of one of the first and second transistors and the collector of the other of the first and second transistors, portions of the first (38, 37) and second (28, 25) connections being doped to correspond to the conductivity type of the base of the collector contacted; first (30b) and second (30a) regions of electrically conductive material deposited on the first (38, 37) and second (28, 25) connections, respectively, to short any PN junctions therein; third (42b, 45b, 47b and fourth (42a, 45a, 47a) regions, each including at least a layer of semiconductor material deposited on the substrate, to contact the base of the first and second transistors, respectively; and fifth (62) and sixth (64) regions of electrically conductive material deposited in contact with selected portions of the third ans fourth regions, respectively, to thereby form first and second Schottky diodes connected to the bases of the first and second transistors, respectively.
Claim 3
Dependent Claim
19 words
A structure as in claim 1 wherein the first (38, 37) and second (28, 25) connections comprise polycrystalline silicon.
Claim 4
Dependent Claim
22 words
A structure as in claim 2 wherein the first and second regions (30b, 30a) of electrically conductive material comprise a metal silicide.
Claim 5
Dependent Claim
31 words
A structure as in anyone of claims 2 and 3 wherein the first (38, 37) and second (28, 25) connections are each doped with both P and N conductivity type impurities.
Claim 6
Dependent Claim
25 words
A structure as in anyone of claims 1 to 4 wherein the fifth and sixth regions (62, 64) of the electrically conductive material comprise metal.
Claim 7
Dependent Claim
23 words
A structure as in claim 4 wherein each of the ; first (38, 37) and second (28, 25) connections includes a PN junction.
Claim 8
Dependent Claim
26 words
A structure as in anyone of claims 1 to 6 wherein the first (12, 17, 58) and second (12, 18) transistors each comprise vertical bipolar transistors.
Claim 9
Dependent Claim
31 words
A structure as in claim 7 wherein each of the first (38, 37) and second (28, 25) connections connect to a base contact (69) in the respective first and second transistors.
Claim 10
Dependent Claim
131 words
A structure as in any of claims 1 to 8, characterized in that said third (42b, 45b, 47b) and fourth (42a, 45a, 47a) regions comprise: first (42b) and second (42a) layers of semiconductor material deposited on the substrate to contact the base of the first and second transistors respectively, third (45b) and fourth (45a) layers of electrically conductive material deposited on the first (42b) and second (42a) layers of semiconductor material respectively; and fifth (47b) and sixth (47a) layers of semiconductor material deposited on the third and fourth layers of electrically conductive material respectively; said fifth (62) and sixth (64) regions of electrically conductive material being deposited in contact with selected portions of the fifth (47b) and sixth (47a) layers of semiconductor material to form said first and second Schottky diodes.
Claim 11
Dependent Claim
49 words
A structure as in claim 9 wherein the first and second layers (42a, 42b) of semiconductor material comprise polycrystalline silicon, the third and fourth layers (45a, 45b) of electrically conductive material comprise a metal silicide, and the fifth and sixth layers (47b), 47a) of semiconductor material comprise polycrystalline silicon.
Claim 12
Dependent Claim
41 words
A structure as in claim 10 wherein the first and second layers (42b, 42a) of semiconductor material are doped with P conductivity type impurity and the fifth and sixth layers (47b, 47a) of semiconductor material are doped with N conductivity impurity.
Claim 13
Dependent Claim
25 words
A structure as in claim 11 wherein emitters (12) of each of the first and second transistors comprise a buried layer in the semiconductor substrate.
Claim 14
Dependent Claim
18 words
A structure as in claim 12 wherein the buried layer (12) is doped with N conductivity type impurities.
Claim 15
Dependent Claim
22 words
A structure as in claim 13 wherein each of the first (12, 17, 58) and second (12, 18) transistors comprise NPN transistors.
Claim 16
Independent Claim
161 words
A method of fabricating integrated circuit memory cells, characterized by comprising: depositing a first layer (23) of semiconductor material across the surface of an underlying semiconductor structure having opposite conductivity type regions; doping the first layer of semiconductor material to correspond to the desired conductivity of the opposite conductivity type regions in the underlying semiconductor structure between which electrical connections are desired; depositing a first electrically conductive layer (30) on the first layer (23) of semiconductor material to short any PN junctions therein; forming insulating material (40) over the first electrically conductive layer; depositing a second layer (42) of semiconductor material over the insulating material (40) and on the underlying semiconductor structure; depositing a second electrically conductive layer (43) on the second layer of semiconductor material; depositing a third layer of semiconductor material (47) on the second electrically conductive layer (45); and depositing metal (62) in contact with selected portions of the third layer of semiconductor material to thereby form diodes.
Claim 17
Independent Claim
161 words
A method of fabricating integrated circuit memory cells, characterized by comprising: depositing a first layer (23) of semiconductor material across the surface of an underlying semiconductor structure having opposite conductivity type regions; doping the first layer of semiconductor material to correspond to the desired conductivity of the opposite conductivity type regions in the underlying semiconductor structure between which electrical connections are desired; depositing a first electrically conductive layer (30) on the first layer (23) of semiconductor material to short any PN junctions therein; forming insulating material (40) over the first electrically conductive layer; depositing a second layer (42) of semiconductor material over the insulating material (40) and on the underlying semiconductor structure; depositing a second electrically conductive layer (43) on the second layer of semiconductor material; depositing a third layer of semiconductor material (47) on the second electrically conductive layer (45); and depositing metal (62) in contact with selected portions of the third layer of semiconductor material to thereby form diodes.
Claim 18
Dependent Claim
24 words
A method as in claim 15, characterized in that the step of depositing the first layer 23 of semiconductor material comprises depositing polycrystalline silicon.
Claim 19
Dependent Claim
20 words
A method as in claim 15 or 16, characterized in that the first electrically conductive layer (30) comprises metal silicide.
Claim 20
Independent Claim
27 words
A method as in anyone of claims 15 to 17, characterized in that the insulating material (40) comprises an oxide of the first layer of semiconductor material.
Claim 21
Independent Claim
36 words
A method as in anyone of claims 15 to 18, characterized in that the second (42) and third (47) layers of semiconductor material comprises polycrystalline silicon and the second electrically conductive layer (45) comprises metal silicide.
Claim 22
Dependent Claim
14 words
A method as in claim 19, characterized in that the metal (62) comprises aluminum.
Claim 23
Dependent Claim
40 words
A method as in claim 19 or 20, characterised in that the second layer (42) of semiconductor material is doped with P conductivity type impurities, and the third layer (47) of semiconductor material is doped with N conductivity type impurities.
Claim 24
Independent Claim
76 words
A method as in anyone of claims 15 to 21, characterized in that, following the step of depositing the first electrically conductive layer (30), a step of patterning the first layer (23) of semiconductor material and the first electrically conductive layer (30) is performed to define two strips (34, 35), each including a portion (25, 28, 37, 38) of the first layer of semiconductor material and a portion (30a, 30b) of the first electrically conductive layer.
Claim 25
Dependent Claim
54 words
A method as in claim 22, characterized in that, following the step of depositing a third layer (47) of semiconductor material, a step of patterning the second and third layers (42, 47) of semiconductor material and the second electrically conductive layer (45) is performed to define those layers into two additional strips (50, 52).
Claim 26
Dependent Claim
55 words
A method as in claim 23, characterized in that the strips (50, 52) comprising the second and third layers (42, 47) of semiconductor material and the second electrically conductive layer (45) are substantially perpendicular to the strips (34, 35) formed from the first layer (23) of semiconductor material and the first electrically conductive layer (30).
Claim 27
Dependent Claim
29 words
A method as in claim 24, characterized in that, following the step of depositing metal (62), a step of patterning the metal into two strips (62, 64) is performed.
Claim 28
Dependent Claim
39 words
A method as in claim 25, characterized in that the two strips (62, 64) of metal are parallel to the two strips (34, 35) comprising the first layer (23) of semiconductor material and the first electrically conductive layer (30).
Claim 29
Independent Claim
121 words
A method as in anyone of claims 15 to 26, characterized in that the step of depositing metal (62) comprises: depositing a layer (48) of selected material on the third layer (47) of semiconductor material; removing the selected material from everywhere on the third layer of semiconductor material except where (48b) the metal (62) is to contact the third layer (47) of semiconductor material; forming a layer of insulating material (56) over all of the third layer of semiconductor material except where (48b) the selected material remains; removing the remaining regions (48b) of selected material; and depositing the metal (62) across the surface of the insulating material (56) and the exposed portions (60, 65) of the third layer of semiconductor material.
Claim 30
Dependent Claim
14 words
A method as in claim 27 wherein the selected material (48) comprises silicon nitride.
References Cited (Backward Citations)
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