US3764825A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Active element memory
Assignee: Individual
•
Filing: 1972-01-10
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Granted: 1973-10-09
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Expires: 1992-01-10
Abstract
Abstract Bistable memory elements having a pair of active transistor components are provided with separate voltage supply lines. The collector and/or emitter circuits of each transistor pair are selectively connected to different ones of the voltage supply lines, which are actuated in sequence to set each memory element into a predetermined initial state, thus combining the advantages of read-only operation with random access capabilities.
Inventors
- 👤 R Stewart
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:29
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4116; G11C14/00; G11C17/00; G11C17/08; G11C7/00; G11C7/20; H03K17/00; H03K17/22; H03K3/2865; H03K2017/226
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
164 words
An active memory cell comprising: a circuit including a pair of active elements each having a control terminal for selectively gating current flow between first and second conduction terminals of each active element connected in series with an associated output impedance between first and second different fixed operating potentials, said first conduction terminal of each active element being coupled to one of said operating potentials through its associated output impedance and cross coupled to the control terminal of the other active element; means coupling the second conduction terminal of both active elements to receive said second operating potential; and means for simultaneously coupling through said associated output impedances the first conduction terminal of one of said active elements to said first operating potential and the first conduction terminal of the other of said active elements to said second operating potential to establish an initial circuit state and for subsequently coupling the first conduction terminal of said other active element to said first operating potential.
Claim 2
Dependent Claim
164 words
An active memory cell comprising: a circuit including a pair of active elements each having a control terminal for selectively gating current flow between first and second conduction terminals of each active element connected in series with an associated output impedance between first and second different fixed operating potentials, said first conduction terminal of each active element being coupled to one of said operating potentials through its associated output impedance and cross coupled to the control terminal of the other active element; means coupling the second conduction terminal of both active elements to receive said second operating potential; and means for simultaneously coupling through said associated output impedances the first conduction terminal of one of said active elements to said first operating potential and the first conduction terminal of the other of said active elements to said second operating potential to establish an initial circuit state and for subsequently coupling the first conduction terminal of said other active element to said first operating potential.
Claim 3
Dependent Claim
52 words
An active memory cell as defined in claim 1 wherein: said pair of active elements comprise a bistable multivibrator adapted to be connected to a voltage supply and said coupling means comprise first and second switches sequentially operable to couple the conduction terminals of said active elements to receive said operating potentials.
Claim 4
Dependent Claim
37 words
An active memory cell as defined in claim 2 wherein: said active elements are transistor elements with said first and second conduction terminals being the collector and emitter terminals, respectively, and said control terminal being the base.
Claim 5
Dependent Claim
230 words
An active memory cell array comprising bistable multivibrators each including: first and second transistor elements, each having its collector connected in series with an associated output impedance and a base terminal for selectively gating current flow between the collector and a plurality of emitters of the respective transistor when said collector in series with its associated output impedance and at least one of the emitters are connected between first and second different operating potentials of a voltage supply source to receive a forward collector to emitter bias, the collector of each transistor being cross coupled to the base of the other transistor; means for selectively coupling the collector of one of said transistor elements through its associated output impedance to The first of said different operating potentials and at least one of the emitters to the second of said different operating potentials to provide said forward collector to emitter bias; sequentially operable switch means for first simultaneously coupling both the collector through said impedance and the emitters of the other of said transistor elements to either of said first or second different operating potentials to establish an initial state and for subsequentially coupling either the collector or receives said first operating potential or at least one emitter of the other transistor to receive said second operating potential to change its operating potential to provide said forward collector to emitter bias.
Claim 6
Dependent Claim
230 words
An active memory cell array comprising bistable multivibrators each including: first and second transistor elements, each having its collector connected in series with an associated output impedance and a base terminal for selectively gating current flow between the collector and a plurality of emitters of the respective transistor when said collector in series with its associated output impedance and at least one of the emitters are connected between first and second different operating potentials of a voltage supply source to receive a forward collector to emitter bias, the collector of each transistor being cross coupled to the base of the other transistor; means for selectively coupling the collector of one of said transistor elements through its associated output impedance to The first of said different operating potentials and at least one of the emitters to the second of said different operating potentials to provide said forward collector to emitter bias; sequentially operable switch means for first simultaneously coupling both the collector through said impedance and the emitters of the other of said transistor elements to either of said first or second different operating potentials to establish an initial state and for subsequentially coupling either the collector or receives said first operating potential or at least one emitter of the other transistor to receive said second operating potential to change its operating potential to provide said forward collector to emitter bias.
Claim 7
Independent Claim
161 words
A method of connecting each bistable circuit in an active memory array to first and second different operating potentials so that each said bistable circuit is driven to a predetermined one of its conducting states, wherein said circuit includes two active elements, each active element having first and second conduction terminals coupled in series with an associated output impedance, the steps of: initially coupling the first and second conduction terminals of one of said active elements in series with its output impedance between said first and second operating potentials respectively; simultaneously coupling both said first and second terminals of the other active element in series with its associated output impedance to either one of said first or second different operating potentials to establish an initial circuit state; and subsequently coupling either the first terminal to receive said first operating potential or said second terminal of said other active element to receive said second operating potential to change the operating potential thereon.
Claim 8
Independent Claim
161 words
A method of connecting each bistable circuit in an active memory array to first and second different operating potentials so that each said bistable circuit is driven to a predetermined one of its conducting states, wherein said circuit includes two active elements, each active element having first and second conduction terminals coupled in series with an associated output impedance, the steps of: initially coupling the first and second conduction terminals of one of said active elements in series with its output impedance between said first and second operating potentials respectively; simultaneously coupling both said first and second terminals of the other active element in series with its associated output impedance to either one of said first or second different operating potentials to establish an initial circuit state; and subsequently coupling either the first terminal to receive said first operating potential or said second terminal of said other active element to receive said second operating potential to change the operating potential thereon.
Claim 9
Dependent Claim
34 words
A method of connecting each bistable circuit as defined in claim 5 wherein: said first potential is a positive potential of a voltage supply and said second potential is a ground or common potential.
Claim 10
Independent Claim
131 words
A method of applying operating potentials from a voltage supply to set each of a plurality of bistable circuits in a desired one of its conducting states, wherein said circuits includes first and second transistor elements, each having base, collector, and emitter terminals, the collector of each transistor being cross coupled to the base of the other transistor, and connected in series with an associated output impedance the steps of: initially coupling the collector of the first transistor through its associated output impedance to a first operating potential; simultaneously coupling the emitters of both transistors and the collector of the second transistor through its associated output impedance to a second operating potential; and, subsequently coupling the collector of the second transistor through its associated output impedance to said first operating potential.
Claim 11
Independent Claim
131 words
A method of applying operating potentials from a voltage supply to set each of a plurality of bistable circuits in a desired one of its conducting states, wherein said circuits includes first and second transistor elements, each having base, collector, and emitter terminals, the collector of each transistor being cross coupled to the base of the other transistor, and connected in series with an associated output impedance the steps of: initially coupling the collector of the first transistor through its associated output impedance to a first operating potential; simultaneously coupling the emitters of both transistors and the collector of the second transistor through its associated output impedance to a second operating potential; and, subsequently coupling the collector of the second transistor through its associated output impedance to said first operating potential.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-08 | 1977-04-09 | 1977-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-08 | 1981-04-09 | 1981-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-08 | 1985-04-09 | 1985-10-09 | $7700.00 | Window Closed / Lapsed |