US3573499A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bipolar memory using stored charge
Assignee: AT&T Inc
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Filing: 1969-05-02
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Granted: 1971-04-06
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Expires: 1989-05-02
Abstract
Abstract A semiconductor memory characterized by simplified memory cells which operate on the charge storage phenomenon. Each cell comprises a pair of cross-coupled transistors, the collector electrodes of which are connected through separate diodes to a pair of information lines. Power is supplied in pulsed fashion via the information lines. No conventional load impedances are used. The coupling diodes prevent discharge of stored information during intervals in which no power is being supplied. The memory advantageously is embodied as a semiconductor integrated circuit.
Inventors
- 👤 Dennis J Lynes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 21:58
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/402; G11C11/4026; G11C11/41; G11C11/411; G11C11/4113; H; H03; H03K; H03K3/00; H03K3/01; H03K3/012
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
148 words
Semiconductor memory apparatus comprising: a plurality of bistable storage cells; means forming a plurality of conduction paths for connecting the cells to circuitry adapted for selectively controlling and sensing the state of each cell; characterized in that each storage cell comprises; a pair of transistors, each having emitter-base, and collector electrodes; means connecting the collector electrode of each transistor to the base electrode of the other transistors; means connecting the emitter electrode of each transistor to the emitter electrode of the other transistor and to one of said conduction paths; separate unilaterally conductive means connected between the collector electrode of each transistor and separate ones of a pair of said conduction paths, said unilaterally conductive means adapted for alternately coupling and decoupling the collector electrodes from the pair of conduction paths; and said cell being free of any load impedances coupled thereto except through the unilaterally conductive means.
Claim 2
Dependent Claim
148 words
Semiconductor memory apparatus comprising: a plurality of bistable storage cells; means forming a plurality of conduction paths for connecting the cells to circuitry adapted for selectively controlling and sensing the state of each cell; characterized in that each storage cell comprises; a pair of transistors, each having emitter-base, and collector electrodes; means connecting the collector electrode of each transistor to the base electrode of the other transistors; means connecting the emitter electrode of each transistor to the emitter electrode of the other transistor and to one of said conduction paths; separate unilaterally conductive means connected between the collector electrode of each transistor and separate ones of a pair of said conduction paths, said unilaterally conductive means adapted for alternately coupling and decoupling the collector electrodes from the pair of conduction paths; and said cell being free of any load impedances coupled thereto except through the unilaterally conductive means.
Claim 3
Dependent Claim
14 words
Apparatus as recited in claim 1 wherein said unilaterally conductive means comprises a diode.
Claim 4
Dependent Claim
29 words
Apparatus as recited in claim 2 wherein the series resistance of the diode is approximately twice the collector series resistance of the transistor to whose collector it is coupled.
Claim 5
Dependent Claim
13 words
Apparatus as recited in claim 2 wherein said diode is a fast-recovery diode.
Claim 6
Dependent Claim
13 words
Apparatus as recited in claim 2 wherein said diode is a Schottky-barrier diode.
Claim 7
Dependent Claim
34 words
Apparatus as recited in claim 1 wherein each of said unilaterally conductive means is poled to pass current in the easy direction from one of said pair of said conduction paths into the cell.
Claim 8
Dependent Claim
48 words
Apparatus as recited in claim 6 wherein each of said unilaterally conductive means comprises a Schottky-barrier diode, the anode of which is connected to one of said pair of said conduction paths and the cathode of which is connected to the collector electrode of one of said transistors.
References Cited (Backward Citations)
US3354440A
Cited
US3492661A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-04-05 | 1974-10-05 | 1975-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-04-05 | 1978-10-05 | 1979-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-04-05 | 1982-10-05 | 1983-04-06 | $7700.00 | Window Closed / Lapsed |