Patent US4845425A successfully refreshed from Google Patents.
US4845425A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Full chip integrated circuit tester
Assignee: International Business Machines Corp
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Filing: 1987-08-11
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Granted: 1989-07-04
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Expires: 2007-08-11
Abstract
Abstract Contactless probing of an integrated circuit is carried out by flooding the surface of the integrated circuit with pulsed ultraviolet laser light, causing photoelectron emission as a function of the potentials at micropoints on the integrated circuit, converting this two-dimensional electron pattern into a corresponding relatively long duration pattern of luminescence by a luminescent target, and reviewing the result by video/computer scanning. Separate embodiments allow testing either in vacuum or in air, with or without insulating passivation layers present on the chip. The result is a contactless oscilloscope which monitors instantaneous voltages (logic states and AC switching waveforms) for a full two-demsnsional array of micropoints simultaneously. A chip with test points and appropriate windows for laser activation and luminescent targeting can be specially designed for optimal testing.
Inventors
- 👤 Johannes G. Beha
- 👤 Russell W. Dreyfus
- 👤 Jeffrey A. Kash
- 👤 Gary W. Rubloff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 22:55
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/302; G01R31/308; G01R31/26; G01R31/265; G01R31/2656
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
152 words
An integrated circuit chip-to-test having enhanced susceptibility to testing by non-contact dynamic photon assisted tunneling testing having a multiplicity of operational circuits of which a testable plurality of such circuits are disposed on a surface comprising: a plurality of test points at identifiable locations on the chip-to-test accessible by photons; a passivation layer covering said plurality of test points and being transparent to laser energy; a luminescent target layer covering said plurality of test points and said passivation layer, and a transparent conductive overlayer disposed over said test points, said passivation layer and said target layer and being transparent to laser energy, wherein said passivation layer and said overlayer are selected such that when the chip-to-test is mounted to operate in a test operational mode and said test points are laser activated during operation, photon assisted tunneling values related to operational parameters are measured from said target layer through said conductive overlayer.
Claim 2
Dependent Claim
152 words
An integrated circuit chip-to-test having enhanced susceptibility to testing by non-contact dynamic photon assisted tunneling testing having a multiplicity of operational circuits of which a testable plurality of such circuits are disposed on a surface comprising: a plurality of test points at identifiable locations on the chip-to-test accessible by photons; a passivation layer covering said plurality of test points and being transparent to laser energy; a luminescent target layer covering said plurality of test points and said passivation layer, and a transparent conductive overlayer disposed over said test points, said passivation layer and said target layer and being transparent to laser energy, wherein said passivation layer and said overlayer are selected such that when the chip-to-test is mounted to operate in a test operational mode and said test points are laser activated during operation, photon assisted tunneling values related to operational parameters are measured from said target layer through said conductive overlayer.
Claim 3
Dependent Claim
32 words
An integrated circuit chip-to-test according to claim 1 further comprising at least one input-output contact designated for test connection; and connection means connecting said test connection to said transparent conductive overlayer (13).
Claim 4
Dependent Claim
36 words
An integrated circuit chip-to-test according to claim 1 wherein said plurality of test points (3) are located in one or more test areas, and optical window openings making available each of said areas to laser light.
Claim 5
Dependent Claim
50 words
An integrated circuit chip-to-test according to claim 1 further comprising luminescent target means (7) disposed between said passivation layer and said overlayer, whereby photoelectron emission from said test points (3) are convertible to relatively long duration luminescence values by said luminescent target means (7) for processing to determine test results.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-03 | 1993-01-02 | 1993-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-03 | 1997-01-02 | 1997-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-03 | 2001-01-02 | 2001-07-04 | $7700.00 | Window Closed / Lapsed |