Patent US4837178A successfully refreshed from Google Patents.
US4837178A
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Method for producing a semiconductor integrated circuit having an improved isolation structure
Assignee: Fujitsu Ltd
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Filing: 1987-09-04
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Granted: 1989-06-06
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Expires: 2007-09-04
Abstract
Abstract A compound semiconductor (e.g., GaAs) IC device structure includes: a compound semiconductor substrate having a semi-insulating compound surface region; an active element laminated layer formed on the surface region; an isolation region of a semi-insulating (intrinsic) compound semiconductor which is filled in a groove extending into the surface region through the laminated layer; and active elements formed in regions of the laminated layer, isolated by the filled groove.
Inventors
- 👤 Toshio Ohshima
- 👤 Naoki Yokoyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:46
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/20; H10D; H10D10/00; H10D10/80; H10D10/821; H10D30/00; H10D30/80; H10D30/87; H10D62/00; H10D62/80; H10D62/82; H10D62/824; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0163; H10D84/02; H10D84/05; H10P14/00; H10P14/20; H10P14/24; H10P14/29; H10P14/2901; H10P14/2907; H10P14/2911; H10P14/32; H10P14/3202; H10P14/3214; H10P14/3221; H10P14/3242; H10P14/3244; H10P14/3251; H10P14/34; H10P14/3402; H10P14/3414; H10P14/3421; H10W; H10W10/00; H10W10/01
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
115 words
A method for producing a semiconductor integrated circuit device comprising the steps of: (a) providing a compound semiconductor substrate having a semi-insulating compound semiconductor surface region; (b) forming an active element laminated layer on the surface region including compound semiconductor layers having a first conductivity type and a second conductivity type opposite the first conductivity type, respectively; (c) forming a groove extending into the surface region by etching portions of the laminated layer and the surface region; (d) filling the groove with a semi-insulating compound semiconductor so as to form an isolation region for electrically isolating active elements from each other; and (e) forming an active element in the isolated regions of the laminated layer.
Claim 2
Independent Claim
115 words
A method for producing a semiconductor integrated circuit device comprising the steps of: (a) providing a compound semiconductor substrate having a semi-insulating compound semiconductor surface region; (b) forming an active element laminated layer on the surface region including compound semiconductor layers having a first conductivity type and a second conductivity type opposite the first conductivity type, respectively; (c) forming a groove extending into the surface region by etching portions of the laminated layer and the surface region; (d) filling the groove with a semi-insulating compound semiconductor so as to form an isolation region for electrically isolating active elements from each other; and (e) forming an active element in the isolated regions of the laminated layer.
Claim 3
Dependent Claim
31 words
A method according to claim 1, wherein said steps a) and b) include forming the compound semiconductor of the surface region and the laminated layer of a Group III-V compound semiconductor.
Claim 4
Dependent Claim
88 words
A method according to claim 2, wherein said step a) includes forming the compound semiconductor of a material selected from the group consisting of Ga x In 1-x AsP 1-x , Ga x Al 1-x As y P 1-y , Ga x Al 1-x As x Sb 1-x , In x Ga y Al 1-x-y P, In x Al 1-x P x As 1-x , In x Al 1-x P x Sb 1-x , and Ga x Al 1-x P x Sb 1-x : wherein 0≦x≦1 and 0≦y≦1.
Claim 5
Dependent Claim
27 words
A method according to claim 1, wherein said step d) includes forming the semi-insulating compound semiconductor of the isolation region of an intrinsic Group III-V compound semiconductor.
Claim 6
Dependent Claim
93 words
A method according to claim 4, wherein said step d) further comprises the substep of forming the intrinsic compound semiconductor of a material selected from the group consisting of Ga x In 1-x As x P 1-x , Ga x Al 1-x As y P 1-y , Ga x Al 1-x As x Sb 1-x , In x Ga y Al 1-x-y P, In x Al 1-x P x As 1-x , InAl 1-x P x Sb 1-x , and Ga x Al 1-x P x Sb 1-x : wherein 0≦x≦1 and 0≦y≦1.
Claim 7
Dependent Claim
100 words
A method according to claim 1, wherein said step b) of forming the active element laminated layer includes the substeps of: (i) forming a collector semiconductor layer having the first conductivity type; (ii) forming a base semiconductor layer having the second conductivity type; and (iii) forming an emitter semiconductor layer having the first conductivity type, and wherein said step e) of forming the active elements includes the substeps of: (i) forming a collector electrode on the collector semiconductor layer; (ii) forming a base electrode on the base semiconductor layer; and (iii) forming an emitter electrode on the emitter semiconductor layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-05 | 1992-12-05 | 1993-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-05 | 1996-12-05 | 1997-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-05 | 2000-12-05 | 2001-06-06 | $7700.00 | Window Closed / Lapsed |