GaAs/GaAlAs Heterojunction bipolar integrated circuit devices

Claim 2

An integrated circuit device comprising: substrate means including at least a body of a first III-V compound semiconductor material of one conductivity type and defining an emitter region;

Claim 3

a first layer of a second III-V compound semiconductor material of the other conductivity type disposed on said body defining said emitter region, said second III-V compound semiconductor material having a bandgap which is smaller than the bandgap of said first III-V compound semiconductor material, said first layer of said second III-V compound semiconductor material of the other conductivity type defining a base region;

Claim 4

a first layer of a second III-V compound semiconductor material of the other conductivity type disposed on said body defining said emitter region, said second III-V compound semiconductor material having a bandgap which is smaller than the bandgap of said first III-V compound semiconductor material, said first layer of said second III-V compound semiconductor material of the other conductivity type defining a base region;

Claim 5

a second layer of said second III-V compound semiconductor material being disposed on said first layer and being of said one conductivity type, said second layer of said second III-V compound semiconductor material of said one conductivity type defining a collector region; and

Claim 6

a second layer of said second III-V compound semiconductor material being disposed on said first layer and being of said one conductivity type, said second layer of said second III-V compound semiconductor material of said one conductivity type defining a collector region; and

Claim 7

electrical contact means respectively coupled to each of said emitter, base and collector regions.

Claim 8

electrical contact means respectively coupled to each of said emitter, base and collector regions.

Claim 9

An integrated circuit device as set forth in claim 1, further including

Claim 10

a dopant implant zone of said other conductivity type extending through said second layer defining said collector region of said one conductivity type and into contact with said first layer defining said base region of said other conductivity type, said dopant implant zone being included as part of said electrical contact means coupled to said base region.

Claim 11

a dopant implant zone of said other conductivity type extending through said second layer defining said collector region of said one conductivity type and into contact with said first layer defining said base region of said other conductivity type, said dopant implant zone being included as part of said electrical contact means coupled to said base region.

Claim 12

An integrated circuit device as set forth in claim 1, further including at least one isolation region extending through said second layer defining said collector region of said one conductivity type and through said first layer defining said base region of said other conductivity type to engage said emitter region of said one conductivity type, said at least one isolation region at least partially surrounding a portion of said base and collector regions to electrically insulate said portion of said base and collector regions from the remainder of said first and second layers of said second III-V compound semiconductor material.

Claim 13

An integrated circuit device as set forth in claim 3, wherein said at least one isolation region comprises a lattice-damaged dopant implant zone extending through said second and first layers.

Claim 14

An integrated circuit device as set forth in claim 2, further including at least one isolation region extending through said second layer defining said collector region of said one conductivity type and through said first layer defining said base region of said other conductivity type to engage said emitter region of said one conductivity type, said at least one isolation region at least partially surrounding a portion of said base and collector regions to electrically insulate said portion of said base and collector regions from the remainder of said first and second layers of said second III-V compound semiconductor material.

Claim 15

An integrated circuit device as set forth in claim 5, wherein said at least one isolation region comprises a lattice-damaged dopant implant zone extending through said second and first layers.

Claim 16

An integrated circuit device as set forth in claim 5, wherein said at least one isolation region is disposed in juxtaposed relation to said dopant implant zone of said other conductivity type.

Claim 17

An integrated circuit device as set forth in claim 7, wherein said at least one isolation region comprises a lattice-damaged dopant implant zone extending through said second and first layers.

Claim 18

An integrated circuit device as set forth in claim 1, wherein said electrical contact means coupled to said collector region includes at least one Schottky barrier metal contact disposed in electrical contact with said collector region to provide a fanout isolation diode.

Claim 19

An integrated circuit device as set forth in claim 9, wherein the thickness of said collector region is one micron or less.

Claim 20

An integrated circuit device as set forth in claim 5, wherein said electrical contact means coupled to said collector region includes at least one Schottky barrier metal contact disposed in electrical contact with said collector region to provide a fanout isolation diode.

Claim 21

An integrated circuit device as set forth in claim 11, wherein said electrical contact means coupled to said collector region further includes first and second ohmic contacts disposed in electrical contact with said collector region and defining a velocity-saturated load element spaced from said fanout isolation diode.

Claim 22

An integrated circuit device as set forth in claim 12, wherein said electrical contact means coupled to said base region further includes an ohmic contact disposed in electrical contact with said dopant implant zone of said other conductivity type; said first and second ohmic contacts disposed in electrical contact with said collector region being spaced from each other to define a resistive path through the portion of said second layer of said second III-V compound semiconductor material defining said collector region which extends therebetween, said resistive path comprising said velocity-saturated load element; and one of said first and second ohmic contacts disposed in electrical contact with said collector region being electrically coupled to said ohmic contact of said electrical contact means coupled to said base region.

Claim 23

An integrated circuit device as set forth in claim 13, wherein the distance of said resistive path between said first and second ohmic contacts disposed in electrical contact with said collector region is determinative of the magnitude of the turn-on voltage to attain saturation current.

Claim 24

An integrated circuit device as set forth in claim 1, further including a dopant implant zone of said other conductivity type extending through said second layer defining said collector region of said one conductivity type and into contact with said first layer defining said base region of said other conductivity type, said dopant implant zone being included as part of said electrical contact means coupled to said base region; at least one isolation region extending through said second layer defining said collector region of said one conductivity type and through said first layer defining said base region of said other conductivity type to engage said emitter region of said one conductivity type, said at least one isolation region being disposed in juxtaposed relation to said dopant implant zone of said other conductivity type and at least partially surrounding a portion of said base and collector regions to electrically insulate said portion of said base and collector regions from the remainder of said first and second layers of said second III-V compound semiconductor material; said electrical contact means coupled to said collector region including first and second ohmic contacts disposed in electrical contact with said collector region and being spaced from each other to define a resistive path through the portion of said second layer of said second III-V compound semiconductor material defining said collector region which extends therebetween, said resistive path comprising a velocity-saturated load element; said electrical contact means coupled to said base region further including an ohmic contact disposed in electrical contact with said dopant implant zone of said other conductivity type; and one of said first and second ohmic contacts disposed in electrical contact with said collector region being electrically coupled to said ohmic contact of said electrical contact means coupled to said base region.

Claim 25

An integrated circuit device as set forth in claim 1, wherein said substrate means comprises a substrate of a crystalline said second III-V compound semiconductor material of said one conductivity type, and said body of said first III-V compound semiconductor material of said one conductivity type defining said emitter region which is disposed on said substrate.

Claim 26

An integrated circuit device as set forth in claim 16, wherein said substrate means further includes a buffer layer of said second III-V compound semiconductor material of said one conductivity type interposed between said substrate and said body defining said emitter region.

Claim 27

An integrated circuit device as set forth in claim 1, wherein said first III-V compound semiconductor material is aluminum gallium arsenide, and said second III-V compound semiconductor material is gallium arsenide.

Claim 28

An integrated circuit device as set forth in claim 18, wherein said one conductivity type is N-type conductivity and said other conductivity type is P-type conductivity such that said emitter region is of N-type conductivity, said base region is of P-type conductivity, and said collector region is of N-type conductivity.

Claim 29

An integrated circuit device as set forth in claim 2, wherein said first III-V compound semiconductor material is aluminum gallium arsenide, and said second III-V compound semiconductor material is gallium arsenide.

Claim 30

An integrated circuit device as set forth in claim 20, wherein said one conductivity type is N-type conductivity and said other conductivity type is P-type conductivity such that said emitter region is of N-type conductivity, said base region is of P-type conductivity, and said collector region is of N-type conductivity.

Claim 31

An integrated circuit device as set forth in claim 3, wherein said first III-V compound semiconductor material is aluminum gallium arsenide, and said second III-V compound semiconductor material is gallium arsenide.

Claim 32

An integrated circuit device as set forth in claim 22, wherein said one conductivity type is N-type conductivity and said other conductivity type is P-type conductivity such that said emitter region is of N-type conductivity, said base region is of P-type conductivity, and said collector region is of N-type conductivity.

Claim 33

An integrated circuit device as set forth in claim 7, wherein said first III-V compound semiconductor material is aluminum gallium arsenide, and said second III-V compound semiconductor material is gallium arsenide.

Claim 34

An integrated circuit device as set forth in claim 24, wherein said one conductivity type is N-type conductivity and said other conductivity type is P-type conductivity such that said emitter region is of N-type conductivity, said base region is of P-type conductivity, and said collector region is of N-type conductivity.

Claim 35

An integrated circuit device as set forth in claim 9, wherein said first III-V compound semiconductor material is aluminum gallium arsenide, and said second III-V compound semiconductor material is gallium arsenide.

Claim 36

An integrated circuit device as set forth in claim 26, wherein said one conductivity type is N-type conductivity and said other conductivity type is P-type conductivity such that said emitter region is of N-type conductivity, said base region is of P-type conductivity, and said collector region is of N-type conductivity.

Claim 37

An integrated circuit device as set forth in claim 13, wherein said first III-V compound semiconductor material is aluminum gallium arsenide, and said second III-V compound semiconductor material is gallium arsenide.

Claim 38

An integrated circuit device as set forth in claim 28, wherein said one conductivity type is N-type conductivity and said other conductivity type is P-type conductivity such that said emitter region is of N-type conductivity, said base region is of P-type conductivity, and said collector region is of N-type conductivity.

Claim 39

An integrated circuit device as set forth in claim 15, wherein said first III-V compound semiconductor material is aluminum gallium arsenide, and said second III-V compound semiconductor material is gallium arsenide.

Claim 40

An integrated circuit device as set forth in claim 30, wherein said one conductivity type is N-type conductivity and said other conductivity type is P-type conductivity such that said emitter region is of N-type conductivity, said base region is of P-type conductivity, and said collector region is of N-type conductivity.