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US4831424A
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Insulated gate semiconductor device with back-to-back diodes
Assignee: Hitachi Ltd
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Filing: 1987-06-15
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Granted: 1989-05-16
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Expires: 2007-06-15
Abstract
Abstract An insulated gate semiconductor device contains a protective element for protecting the gate electrode of an insulated gate field effect transistor. The protective element is formed of the same semiconductor layer as that of the gate electrode of the insulated gate field effect transistor and is formed integrally with the gate electrode on an insulating film formed on the surface of a semiconductor substrate.
Inventors
- 👤 Isao Yoshida
- 👤 Takeaki Okabe
- 👤 Mitsuo Ito
- 👤 Kazutoshi Ashikawa
- 👤 Tetsuo Iijima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:47
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/101; H10D84/141; H10D84/148; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D30/665; H10D89/00; H10D89/60; H10D89/601; H10D89/611; H10D62/00; H10D62/10; H10D62/124; H10D62/126; H10D8/00; H10D8/20; H10D8/25
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
346 words
An insulated gate semiconductor device comprising an insulated gate field effect transistor and a protective element portion for protecting the gate insulating film of said transistor, said transistor comprising: a semiconductor body of a first conductivity type, said semiconductor body having an upper surface portion and a lower surface portion, wherein said semiconductor body serves as a drain region; a first region of a second conductivity type, opposite to said first conductivity type, serving as a channel portion, selectively formed in said upper surface portion of said body; a second region of said first conductivity type serving as a source region selectively formed in said first region; a gate insulating film disposed on the surface portion of said first region between said second region and said semiconductor body; a first polycrystalline silicon layer serving as a gate electrode disposed on said gate insulating film and overlaying said channel portion therebeneath; a source electrode disposed on said second region; and a drain electrode portion disposed on said lower surface portion; and said protective element portion comprising: a third region of said second conductivity type selectively formed in another portion of said semiconductor body and separated from the first region; a field insulating film disposed on the surface portion of said third region; a second polycrystalline silicon layer disposed on said field insulating film; and a plurality of regions of opposite conductivity to one another formed in said second polycrystalline silicon layer and arranged relative to one another to provide a plurality of PN junctions in said second polycrystalline silicone layer, wherein said first and second polycrystalline silicon layers are formed integrally with each other, wherein a thickness of said field insulating film is thicker than a thickness of said gate insulating film to reduce a field effect influence on said protective element by said drain region, and further wherein said third region is located to be interposed between at least a portion of said gate elcctrode and at least a portion of said drain electrode to reduce parasitic capacitance between said gate electrode and said drain electrode.
Claim 2
Dependent Claim
346 words
An insulated gate semiconductor device comprising an insulated gate field effect transistor and a protective element portion for protecting the gate insulating film of said transistor, said transistor comprising: a semiconductor body of a first conductivity type, said semiconductor body having an upper surface portion and a lower surface portion, wherein said semiconductor body serves as a drain region; a first region of a second conductivity type, opposite to said first conductivity type, serving as a channel portion, selectively formed in said upper surface portion of said body; a second region of said first conductivity type serving as a source region selectively formed in said first region; a gate insulating film disposed on the surface portion of said first region between said second region and said semiconductor body; a first polycrystalline silicon layer serving as a gate electrode disposed on said gate insulating film and overlaying said channel portion therebeneath; a source electrode disposed on said second region; and a drain electrode portion disposed on said lower surface portion; and said protective element portion comprising: a third region of said second conductivity type selectively formed in another portion of said semiconductor body and separated from the first region; a field insulating film disposed on the surface portion of said third region; a second polycrystalline silicon layer disposed on said field insulating film; and a plurality of regions of opposite conductivity to one another formed in said second polycrystalline silicon layer and arranged relative to one another to provide a plurality of PN junctions in said second polycrystalline silicone layer, wherein said first and second polycrystalline silicon layers are formed integrally with each other, wherein a thickness of said field insulating film is thicker than a thickness of said gate insulating film to reduce a field effect influence on said protective element by said drain region, and further wherein said third region is located to be interposed between at least a portion of said gate elcctrode and at least a portion of said drain electrode to reduce parasitic capacitance between said gate electrode and said drain electrode.
Claim 3
Dependent Claim
33 words
An insulated gate semiconductor device according to claim 1, wherein said plurality of PN junctions are configured in substantially concentric ring-like shapes from the perspective of the upper surface of the semiconductor body.
Claim 4
Dependent Claim
22 words
An insulated gate semiconductor device according to claim 1, further comprising means for electrically connecting said third region to said second region.
Claim 5
Dependent Claim
34 words
An insulated gate semiconductor device according to claim 1, wherein said plurality of PN junctions are configured in substantially concentric closed-loop serpentine shapes from the perspective of the upper surface of the semiconductor body.
Claim 6
Dependent Claim
326 words
A semiconductor device having both a vertical MOSFET and a protective element for protecting a gate oxide film in said vertical MOSFET, said semiconductor device comprising: a semiconductor substrate of a first conductivity type serving as a drain region of said vertical MOSFET, said semiconductor substrate having an upper surface portion and a lower surface portion; a first region of a second conductivity type, opposite to said first conductivity type, serving as a channel portion of said vertical MOSFET, said first region being selectively formed at said upper surface portion of said semiconductor substrate; a second region of said first conductivity type serving as a source region of said vertical MOSFET, said second region being selectively formed in said first region; said gate oxide film of said vertical MOSFET disposed on the surface portion of said first region between said second region and said semiconductor substrate; a gate electrode of said vertical MOSFET which is made of a first polycrystalline silicon layer, said gate electrode being formed on said gate oxide film so that the channel portin of said vertical MOSFET in said first region is overlaid with said gate electrode; a source electrode disposed on said second region; a drain electrode portion disposed on said lower surface portion of said semiconductor substrate; a third region of said second conductivity type selectively formed in said upper surface portion of said semiconductor substrate and separated from the first region; and a field oxide film disposed on the surface portion of said third region, wherein a thickness of said field oxide film is thicker than a thickness of said gate oxide film, wherein said protective element is formed on said field oxide film, said protective element comprising a second polycrystalline silicon layer having a plurality of PN junctions, wherein said protective element is coupled between said gate electrode and said source electrode, and further wherein said first and second polycrystalline silicon layers are formed integrally with each other.
Claim 7
Dependent Claim
326 words
A semiconductor device having both a vertical MOSFET and a protective element for protecting a gate oxide film in said vertical MOSFET, said semiconductor device comprising: a semiconductor substrate of a first conductivity type serving as a drain region of said vertical MOSFET, said semiconductor substrate having an upper surface portion and a lower surface portion; a first region of a second conductivity type, opposite to said first conductivity type, serving as a channel portion of said vertical MOSFET, said first region being selectively formed at said upper surface portion of said semiconductor substrate; a second region of said first conductivity type serving as a source region of said vertical MOSFET, said second region being selectively formed in said first region; said gate oxide film of said vertical MOSFET disposed on the surface portion of said first region between said second region and said semiconductor substrate; a gate electrode of said vertical MOSFET which is made of a first polycrystalline silicon layer, said gate electrode being formed on said gate oxide film so that the channel portin of said vertical MOSFET in said first region is overlaid with said gate electrode; a source electrode disposed on said second region; a drain electrode portion disposed on said lower surface portion of said semiconductor substrate; a third region of said second conductivity type selectively formed in said upper surface portion of said semiconductor substrate and separated from the first region; and a field oxide film disposed on the surface portion of said third region, wherein a thickness of said field oxide film is thicker than a thickness of said gate oxide film, wherein said protective element is formed on said field oxide film, said protective element comprising a second polycrystalline silicon layer having a plurality of PN junctions, wherein said protective element is coupled between said gate electrode and said source electrode, and further wherein said first and second polycrystalline silicon layers are formed integrally with each other.
Claim 8
Dependent Claim
338 words
A semiconductor device having both a vertical MOSFET and a protective element for protecting a gate oxide film in said vertical MOSFET, said semiconductor device comprising: a semiconductor substrate of a first conductivity type serving as a drain region of said vertical MOSFET, said semiconductor substrate having an upper surface portion and a lower surface portion; a first region of a second conductivity type, opposite to said first conductivity type, serving as a channel portion of said vertical MOSFET, said first region being selectively formed at said upper surface portion of said semiconductor substrate; a second region of said first conductivity type serving as a source region of said vertical MOSFET, said second region being selectively formed in said first region; said gate oxide film of said vertical MOSFET being disposed on the surface portion of said first region between said second region and said semiconductor substrate; a gate electrode of said vertical MOSFET which is comprised of a first polycrystalline silicon layer, said gate electrode being formed on said gate oxide film so that the channel portion of said vertical MOSFET in said first region is overlaid with said gate electrode; a source electrode disposed on said second region; a drain electrode portion disposed on said lower surface portion of said semiconductor substrate; a third region of said second conductivity type selectively formed in said upper surface portion of said semiconductor substrate and separated from the first region; means for electrically connecting said third region to said second region; and a field oxide film disposed on the surface portion of said third region, wherein a thickness of said field oxide film is thicker than a thickness of said gate oxide film, wherein said protective element is formed on said field oxide film, said protective element comprising a second polycrystalline silicon layer having a plurality of PN junctions, wherein said protective element is coupled between said gate electrode and said source electrode, and further wherein said first and second polycrystalline silicon layers are formed integrally with each other.
Claim 9
Dependent Claim
338 words
A semiconductor device having both a vertical MOSFET and a protective element for protecting a gate oxide film in said vertical MOSFET, said semiconductor device comprising: a semiconductor substrate of a first conductivity type serving as a drain region of said vertical MOSFET, said semiconductor substrate having an upper surface portion and a lower surface portion; a first region of a second conductivity type, opposite to said first conductivity type, serving as a channel portion of said vertical MOSFET, said first region being selectively formed at said upper surface portion of said semiconductor substrate; a second region of said first conductivity type serving as a source region of said vertical MOSFET, said second region being selectively formed in said first region; said gate oxide film of said vertical MOSFET being disposed on the surface portion of said first region between said second region and said semiconductor substrate; a gate electrode of said vertical MOSFET which is comprised of a first polycrystalline silicon layer, said gate electrode being formed on said gate oxide film so that the channel portion of said vertical MOSFET in said first region is overlaid with said gate electrode; a source electrode disposed on said second region; a drain electrode portion disposed on said lower surface portion of said semiconductor substrate; a third region of said second conductivity type selectively formed in said upper surface portion of said semiconductor substrate and separated from the first region; means for electrically connecting said third region to said second region; and a field oxide film disposed on the surface portion of said third region, wherein a thickness of said field oxide film is thicker than a thickness of said gate oxide film, wherein said protective element is formed on said field oxide film, said protective element comprising a second polycrystalline silicon layer having a plurality of PN junctions, wherein said protective element is coupled between said gate electrode and said source electrode, and further wherein said first and second polycrystalline silicon layers are formed integrally with each other.
Claim 10
Dependent Claim
283 words
A semiconductor device comprising an MOS transistor and a protective element portion for protecting the gate oxide film of said transistor, said transistor comprising: a semiconductor body of a first conductivity type serving as a drain region, said semiconductor body having an upper surface portion and a lower surface portion; a first region of a second conductivity type, opposite to said first conductivity type, serving as a channel portion, selectively formed in said upper surface portion of said body; a second region of said first conductivity type serving as a source region in said first region; said gate oxide film being disposed on a surface portion of said first region between said second region and said semiconductor body; a first polycrystalline silicon layer serving as a gate electrode disposed on said gate oxide film and overlaying said channel portion therebeneath; a source electrode disposed on said second region; and a drain electrode portion disposed on said lower surface portion; and said protective element portion comprising: a third region of said second conductivity type selectively formed in another portion of said semiconductor body and separated from the first region; and a field oxide film disposed on a surface portion of said third region; second polycrystalline silicon layer disposed on said field oxide film; and a plurality of regions of opposite conductivity type to one another formed in said second polycrystalline silicon layer and arranged relative to one another to provide a plurality of PN junctions in said second polycrystalline silicon layer, wherein said first and second polycrystalline silicon layers are formed integrally with each other, and wherein a thickness of said field oxide film is thicker than a thickness of said gate oxide film.
Claim 11
Dependent Claim
283 words
A semiconductor device comprising an MOS transistor and a protective element portion for protecting the gate oxide film of said transistor, said transistor comprising: a semiconductor body of a first conductivity type serving as a drain region, said semiconductor body having an upper surface portion and a lower surface portion; a first region of a second conductivity type, opposite to said first conductivity type, serving as a channel portion, selectively formed in said upper surface portion of said body; a second region of said first conductivity type serving as a source region in said first region; said gate oxide film being disposed on a surface portion of said first region between said second region and said semiconductor body; a first polycrystalline silicon layer serving as a gate electrode disposed on said gate oxide film and overlaying said channel portion therebeneath; a source electrode disposed on said second region; and a drain electrode portion disposed on said lower surface portion; and said protective element portion comprising: a third region of said second conductivity type selectively formed in another portion of said semiconductor body and separated from the first region; and a field oxide film disposed on a surface portion of said third region; second polycrystalline silicon layer disposed on said field oxide film; and a plurality of regions of opposite conductivity type to one another formed in said second polycrystalline silicon layer and arranged relative to one another to provide a plurality of PN junctions in said second polycrystalline silicon layer, wherein said first and second polycrystalline silicon layers are formed integrally with each other, and wherein a thickness of said field oxide film is thicker than a thickness of said gate oxide film.
Claim 12
Dependent Claim
34 words
An insulated gate semiconductor device according to claim 5, wherein said plurality of PN junctions are configured in substantially concentric ring-like shapes from the perspective of the upper surface portion of the semiconductor substrate.
Claim 13
Dependent Claim
35 words
An insulated gate semiconductor device according to claim 5, wherein said plurality of PN junctions are configured in substantially concentric closed-loop serpentine shapes from the perspective of the upper surface portion of the semiconductor substrate.
Claim 14
Dependent Claim
34 words
An insulated gate semiconductor device according to claim 6, wherein said plurality of PN junctions are configured in substantially concentric ring-like shapes from the perspective of the upper surface portion of the semiconductor substrate.
Claim 15
Dependent Claim
35 words
An insulated gate semiconductor device according to claim 6, wherein said plurality of PN junctions are configured in substantially concentric closed-loop serpentine shapes from the perspective of the upper surface portion of the semiconductor substrate.
Claim 16
Dependent Claim
34 words
An insulated gate semiconductor device according to claim 7, wherein said plurality of PN junctions are configured in substantially concentric ring-like shapes from the perspective of the upper surface portion of the semiconductor substrate.
Claim 17
Dependent Claim
35 words
An insulated gate semiconductor device according to claim 7, wherein said plurality of PN junctions are configured in substantially concentric closed-loop serpentine shapes from the perspective of the upper surface portion of the semiconductor substrate.
Claim 18
Dependent Claim
22 words
An insulated gate semiconductor device according to claim 7, further comprising means for electrically connecting said third region to said second region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-15 | 1992-11-14 | 1993-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-15 | 1996-11-14 | 1997-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-15 | 2000-11-14 | 2001-05-16 | $7700.00 | Window Closed / Lapsed |