Patent US4830976A successfully refreshed from Google Patents.
US4830976A
Expired / Lapsed
US
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Integrated circuit resistor
Assignee: Nokia Bell Labs
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Filing: 1987-02-24
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Granted: 1989-05-16
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Expires: 2007-02-24
Abstract
Abstract An integrated circuit comprises a resistor that is formed by doping a semiconductor region that is defined by a layer, typically polysilicon, that also defines the gate electrode of field effect transistors in the integrated circuit. The well-controlled linewidth of features defined in this layer provides for tight resistor tolerance, and also allows the value of the resistor to track changes in other features defined by this layer.
Inventors
- 👤 Bernard L. Morris
- 👤 Jeffrey J. Nagy
- 👤 Lawrence A. Walter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:23
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/26; G05F3/262
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
112 words
A method of making an integrated circuit including the step of forming at least one resistor in said integrated circuit, by steps comprising: forming a layer of conductive material overlying a semiconductor body; forming a pattern in said layer that defines the gate electrode of at least one field effect transistor formed in said semiconductor body; and introducing a dopant into said semiconductor body; characterized in that said layer as patterned includes an opening that allows said dopant to be introduced into a resistor region of said semiconductor body, and said layer as patterned prevents said dopant from being introduced into the region of said semiconductor body immediately surrounding said resistor region.
Claim 2
Independent Claim
112 words
A method of making an integrated circuit including the step of forming at least one resistor in said integrated circuit, by steps comprising: forming a layer of conductive material overlying a semiconductor body; forming a pattern in said layer that defines the gate electrode of at least one field effect transistor formed in said semiconductor body; and introducing a dopant into said semiconductor body; characterized in that said layer as patterned includes an opening that allows said dopant to be introduced into a resistor region of said semiconductor body, and said layer as patterned prevents said dopant from being introduced into the region of said semiconductor body immediately surrounding said resistor region.
Claim 3
Dependent Claim
10 words
The method of claim 1 wherein said material comprises silicon.
Claim 4
Dependent Claim
15 words
The method of claim 2 wherein said silicon is in the form of polycrystalline silicon.
Claim 5
Dependent Claim
12 words
The method of claim 1 wherein said material comprises a metal silicide.
Claim 6
Dependent Claim
12 words
The method of claim 1 wherein said material comprises a refractory metal.
References Cited (Backward Citations)
US3328685A
Cited
US3483464A
Cited
US3759762A
Cited
US3860465A
Cited
US3813595A
Cited
US3875430A
Cited
US4009432A
Cited
US4053915A
Cited
US4051392A
Cited
US4110776A
Cited
US4207537A
Cited
US4287438A
Cited
JPS5643749A
Cited
JPS5683964A
Cited
US4419808A
Cited
US4554729A
Cited
JPS58166757A
Cited
JPS59161857A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-15 | 1992-11-14 | 1993-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-15 | 1996-11-14 | 1997-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-15 | 2000-11-14 | 2001-05-16 | $7700.00 | Window Closed / Lapsed |