US3759762A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming integrated circuits utilizing low resistance valueslow temperature deposited oxides and shallow junctions
Assignee: Motorola Solutions Inc
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Filing: 1970-10-19
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Granted: 1973-09-18
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Expires: 1990-10-19
Abstract
Abstract A SEMICONDUCTOR STRUCTURE IS DESCRIBED WHEREIN INTEGRALLY FORMED RESISTORS ARE EMPLOYED HAVING A PREFERRED RESISTANCE VALUE OF APPROXIMATELY 50 OHMS PER SQUARE. ADDITIONALLY, PROCESSING IS COMPATIBLE WITH THIS LOW RESISTANCE VALUE AND INCLUDES LOW TEMPERATURE DEPOSITION OF PASSIVATING LAYERS, IMPROVED CLEANING AND ANNEALING CYCLES.
Inventors
- 👤 F Barone
- 👤 D Tolliver
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 06:32
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/43; H10D1/01; H10D1/025; H10D99/00; H10P; H10P95/00; Y; Y10; Y10S; Y10S148/00; Y10S148/017; Y10S148/043; Y10S148/049; Y10S148/06; Y10S148/118; Y10S148/173
Claims Analysis
Total Claims: 0
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References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-17 | 1977-03-19 | 1977-09-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-17 | 1981-03-19 | 1981-09-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-17 | 1985-03-19 | 1985-09-18 | $7700.00 | Window Closed / Lapsed |