Patent US4827160A successfully refreshed from Google Patents.
US4827160A
Expired / Lapsed
US
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Dynamic decoder circuit with charge-sharing prevention means
Assignee: Fujitsu Ltd
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Filing: 1988-03-10
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Granted: 1989-05-02
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Expires: 2008-03-10
Abstract
Abstract A dynamic type decoder circuit including a first power source line; a second power source line; and output node; a first transistor connected between the first power source line and the output node, the first transistor being turned on during a reset period to reset the output potential of the output node to a predetermined potential level; a second transistor connected to a second power source line, the second transistor being turned on during a decoding period; a plurality of decoding transistors connected in series between the output node and the second transistor, the decoding transistors being controlled in accordance with address signals; and means for forcibly turning on one or more decoding transistors connected between the output node and the decoding transistor directly connected to the second transistor during the reset period regardless of the potential levels of the address signals.
Inventors
- 👤 Yoshiaki Okano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 05:16
CPC Classifications
G; G11; G11C; G11C7/00; G11C8/00; G11C8/10; G11C8/06
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
148 words
A dynamic type decoder circuit comprising: a first power source line; a second power source line; an output node; a first transistor connected between said first power source line and said output node, said first transistor being turned on during a reset period to reset the output potential of said output node to a predetermined potential level; a second transistor connected to said second power source line, said second transistor being turned on during a decoding period; a plurality of decoding transistors connected in series between said output node and said second transistor, said plurality of decoding transistors being controlled in accordance with address signals; and means for forcibly turning on one or more of said plurality of decoding transistors connected between said output node and the decoding transistor directly connected to said second transistor during said reset period regardless of the potential levels of said address signals.
Claim 2
Dependent Claim
148 words
A dynamic type decoder circuit comprising: a first power source line; a second power source line; an output node; a first transistor connected between said first power source line and said output node, said first transistor being turned on during a reset period to reset the output potential of said output node to a predetermined potential level; a second transistor connected to said second power source line, said second transistor being turned on during a decoding period; a plurality of decoding transistors connected in series between said output node and said second transistor, said plurality of decoding transistors being controlled in accordance with address signals; and means for forcibly turning on one or more of said plurality of decoding transistors connected between said output node and the decoding transistor directly connected to said second transistor during said reset period regardless of the potential levels of said address signals.
Claim 3
Dependent Claim
38 words
A dynamic type decoder circuit according to claim 1, further comprising means for forcibly turning on said decoding transistor directly connected to said second transistor during said reset period regardless of the potential levels of said address signals.
Claim 4
Dependent Claim
96 words
A dynamic type decoder circuit according to claim 1, further comprising a plurality of other decoding transistors connected in series between said output node and said second transistor and connected in parallel with said plurality of decoding transistors, said plurality of other decoding transistors being controlled in accordance with address signals; and means for forcibly turning on one or more of said plurality of other decoding transistors connected between said output node and the other decoding transistor directly connected to said second transistor during said reset period regardless of the potential levels of said address signals.
Claim 5
Dependent Claim
43 words
A dynamic type decoder circuit according to claim 3, further comprising means for forcibly turning on said decoding transistor and said other decoding transistor directly connected to said second transistor during said reset period regardless of the potential levels of said address signals.
Claim 6
Dependent Claim
103 words
A dynamic type decoder circuit according to claim 1, wherein said first transistor and said second transistor are a P-channel type transistor and an N-channel type transistor, respectively, and said means for forcibly turning transistors on comprises one or more inverters each receiving one of the address signals and one or more NAND gates each receiving a clock signal supplied to said first transistor and the output signal from one of said inverters, each output signal of said NAND gates being supplied to one of said decoding transistors connected between said output node and said decoding transistor directly connected to said second transistor.
Claim 7
Dependent Claim
103 words
A dynamic type decoder circuit according to claim 1, wherein said first transistor and said second transistor are an N-channel type transistor and a P-channel type transistor, respectively, and said means for forcibly turning transistors on comprises one or more inverters each receiving one of the address signals and one or more NOR gates each receiving a clock signal supplied to said first transistor and the output signal from one of said inverters, each output signal of said NOR gates being supplied to one of said decoding transistors connected between said output node and said decoding transistor directly connected to said second transistor.
Claim 8
Dependent Claim
97 words
A dynamic type decoder circuit according to claim 2, wherein said first transistor and said second transistor are a P-channel type transistor and an N-channel type transistor, respectively, and said means for forcibly turning transistors on comprises a plurality of inverters each receiving one of the address signals and a plurality of NAND gates each receiving a clock signal supplied to said first transistor and the output signal from one of said inverters, each output signal of said NAND gates being supplied to one of said decoding transistors connected between said output node and said second transistor.
Claim 9
Dependent Claim
97 words
A dynamic type decoder circuit according to claim 2, wherein said first transistor and said second transistor are an N-channel type transistor and a P-channel type transistor, respectively, and said means for forcibly turning transistors on comprises a plurality of inverters each receiving one of the address signals and a plurality of NOR gates each receiving a clock signal supplied to said first transistor and the output signal from one of said inverters, each output signal of said NOR gates being supplied to one of said decoding transistors connected between said output node and said second transistor.
Claim 10
Dependent Claim
116 words
A dynamic type decoder circuit according to claim 3, wherein said first transistor and said second transistor are a P-channel type transistor and an N-channel type transistor, respectively, and said means for forcibly turning transistors on comprises one or more inverters each receiving one of the address signals and one or more NAND gates each receiving a clock signal supplied to said first transistor and the output signal from one of said inverters, each output signal of said NAND gates being supplied to one of said decoding transistors and said other decoding transistors each connected between said output node and one of said decoding transistor and said other decoding transistor directly connected to said second transistor.
Claim 11
Dependent Claim
116 words
A dynamic type decoder circuit according to claim 3, wherein said first transistor and said second transistor are an N-channel type transistor and a P-channel type transistor, respectively, and said means for forcibly turning transistors on comprises one or more inverters each receiving one of the address signals and one or more NOR gates each receiving a clock signal supplied to said first transistor and the output signal from one of said inverters, each output signal of said NOR gates being supplied to one of said decoding transistors and said other decoding transistors each connected between said output node and one of said decoding transistor and said other decoding transistor directly connected to said second transistor.
Claim 12
Dependent Claim
103 words
A dynamic type decoder circuit according to claim 4, wherein said first transistor and said second transistor are a P-channel type transistor and an N-channel type transistor, respectively, and said means for forcibly turning transistors on comprises a plurality of inverters each receiving one of the address signals and a plurality of NAND gates each receiving a clock signal supplied to said first transistor and the output signal from one of said inverters, each output signal of said NAND gates being supplied to one of said decoding transistors and said other decoding transistors each connected between said output node and said second transistor.
Claim 13
Dependent Claim
103 words
A dynamic type decoder circuit according to claim 4, wherein said first transistor and said second transistor are an N-channel type transistor and a P-channel type transistor, respectively, and said means for forcibly turning transistors on comprises a plurality of inverters each receiving one of the address signals and a plurality of NOR gates each receiving a clock signal supplied to said first transistor and the output signal from one of said inverters, each output signal of said NOR gates being supplied to one of said decoding transistors and said other decoding transistors each connected between said output node and said second transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-01 | 1992-10-31 | 1993-05-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-01 | 1996-10-31 | 1997-05-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-01 | 2000-10-31 | 2001-05-02 | $7700.00 | Window Closed / Lapsed |