Patent US4823029A successfully refreshed from Google Patents.
US4823029A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Noise controlled output buffer
Assignee: Nokia Bell Labs
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Filing: 1987-06-25
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Granted: 1989-04-18
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Expires: 2007-06-25
Abstract
Abstract An integrated circuit has output buffers whose switching rise and/or fall times are controlled to compensate for process speed and other variations. Therefore, an integrated circuit fabricated by a "fast" process does not generate excessive noise, while integrated circuits fabricated by a "slow" process still obtain adequate speed. A control voltage generated by an on-chip voltage divider network is applied to the gate of a control transistor to provide the compensation.
Inventors
- 👤 Thaddeus J. Gabara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:48
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/16; H03K17/161; H03K17/162; H03K17/163; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
187 words
An integrated circuit comprising at least one output buffer having an input (IN) for receiving a logical signal and an output (OUT) for driving a conductor with said signal, wherein said buffer comprises at least one input transistor having its gate coupled to said input, and further comprises at least one output transistor having its gate coupled to the drain of said input transistor, and a controlled electrode coupled to said output, characterized in that said output buffer further comprises a control transistor included in the source path of said at least one input transistor, wherein said integrated circuit further comprises means for generating a control voltage applied to the gate of said control transistor, with said control voltage decreasing the conductance of said control transistor when said integrated circuit is fabricated by a process that yields transistor switching speeds faster than a nominal process, wherein said control voltage is derived from the node connecting the drain of a first voltage divider transistor and a resistor coupled to a power supply voltage conductor, and wherein said first voltage divider transistor has its gate connected to its drain.
Claim 2
Dependent Claim
187 words
An integrated circuit comprising at least one output buffer having an input (IN) for receiving a logical signal and an output (OUT) for driving a conductor with said signal, wherein said buffer comprises at least one input transistor having its gate coupled to said input, and further comprises at least one output transistor having its gate coupled to the drain of said input transistor, and a controlled electrode coupled to said output, characterized in that said output buffer further comprises a control transistor included in the source path of said at least one input transistor, wherein said integrated circuit further comprises means for generating a control voltage applied to the gate of said control transistor, with said control voltage decreasing the conductance of said control transistor when said integrated circuit is fabricated by a process that yields transistor switching speeds faster than a nominal process, wherein said control voltage is derived from the node connecting the drain of a first voltage divider transistor and a resistor coupled to a power supply voltage conductor, and wherein said first voltage divider transistor has its gate connected to its drain.
Claim 3
Dependent Claim
20 words
The integrated circuit of claim 1 comprising both p-channel and n-channel output transistors having their sources connected to said output.
Claim 4
Dependent Claim
55 words
The integrated circuit of claim 2 comprising both p-channel and n-channel input transistors having their gates coupled to said input, wherein a control transistor is included in the source paths of both of said input transistors, whereby control of both the rise time and the fall time of said signal at said output is obtained.
Claim 5
Dependent Claim
26 words
The integrated circuit of claim 1 wherein a tri-state transistor is connected between the source of said input transistor and the drain of said control transistor.
Claim 6
Dependent Claim
45 words
The integrated circuit of claim 1 wherein a tri-state transistors is connected between the gate of said output transistor and the drain of said input transistor, with said control transistor being connected between the source of said input transistor and a power supply voltage conductor.
Claim 7
Dependent Claim
48 words
The integrated circuit of claim 1 wherein said control voltage is further derived from the node connecting the drain of a second voltage divider transistor and a resistor coupled to a power supply voltage conductor, wherein said second voltage divider transistor has its gate connected to its drain.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-17 | 1992-10-17 | 1993-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-17 | 1996-10-17 | 1997-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-17 | 2000-10-17 | 2001-04-18 | $7700.00 | Window Closed / Lapsed |