US4346343A
Expired / Lapsed
US
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Power control means for eliminating circuit to circuit delay differences and providing a desired circuit delay
Assignee: International Business Machines Corp
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Filing: 1980-05-16
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Granted: 1982-08-24
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Expires: 2000-05-16
Abstract
Abstract An on chip delay regulator circuit which varies the power in logic or array circuits on the chip so as to minimize, or eliminate, chip to chip circuit speed differences caused by power supply variations and/or lot to lot process differences, temperature, etc. The on chip delay regulator accomplishes this by comparing a reference signal to an on chip generated signal which is sensitive to power supply changes, lot to lot process changes, temperature, etc. The comparison creates an error signal which is used to change the power (current or voltage) supplied to the on chip circuits. By changing the circuit power, the circuit speed (gate delay) is increased or decreased as necessary to maintain a relatively constant circuit speed on each chip. For example, a plurality of integrated circuit chips each contain an on chip delay regulator. The on chip delay regulator on each chip of said plurality of integrated circuit chips receives and responds to the same signal (or clock). Each chip provides a discrete on chip generated signal related to the parameters of the chip. The gate delay (or speed) of the circuitry on each chip is determined by its on chip delay regulator under control of the common reference signal (or clock).
Inventors
- 👤 Erich Berndlmaier
- 👤 Jack A. Dorler
- 👤 Joseph M. Mosley
- 👤 Stephen D. Weitzel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:37
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; G; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/462; G05F1/466; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/03; H03K3/0315; H03K3/0322; H03L7/099; H03L7/0995; H03L7/085; H03L7/089
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
110 words
In an electronic system including one or more interconnected integrated circuit chips, each of said one or more integrated circuit chips having a plurality of interconnected logic circuits thereon, each of said logic circuits having a gate delay versus power curve, said system being characterized by the inclusion of power control means for regulating the power to each of said one or more chips whereby the power provided to said logic circuits on said one or more integrated circuit chips may vary chip to chip but said gate delay of said logic circuits on each of said one or more integrated circuit chips will be essentially equal one to another.
Claim 2
Dependent Claim
110 words
In an electronic system including one or more interconnected integrated circuit chips, each of said one or more integrated circuit chips having a plurality of interconnected logic circuits thereon, each of said logic circuits having a gate delay versus power curve, said system being characterized by the inclusion of power control means for regulating the power to each of said one or more chips whereby the power provided to said logic circuits on said one or more integrated circuit chips may vary chip to chip but said gate delay of said logic circuits on each of said one or more integrated circuit chips will be essentially equal one to another.
Claim 3
Dependent Claim
49 words
In an electronic system including one or more interconnected integrated circuit chips, as recited in claim 1, wherein said system is further characterized in that said power control means consists of a discrete delay regulator means contained on each chip of said one or more interconnected integrated circuit chips.
Claim 4
Dependent Claim
83 words
In an electronic system including one or more interconnected integrated circuit chips, as recited in claim 2, wherein said system is further characterized in that each of said discrete delay regulators is adapted to receive a periodic clock pulse and generate an on chip periodic pulse, said generated on chip periodic pulse having a periodicity related to a point on said gate delay versus power curve of the logic circuits on the chip on which said generated on chip periodic pulse is generated.
Claim 5
Dependent Claim
56 words
In an electronic system including one or more interconnected integrated circuit chips, as recited in claim 3, further characterized in that each of said discrete delay regulator means compares said period clock pulse with its on chip generated periodic pulse and provides an electrical manifestation representative of the result of the comparison of said periodic pulses.
Claim 6
Dependent Claim
43 words
In an electronic system including one or more interconnected integrated circuit chips, as recited in claim 4, wherein said system is further characterized in that each of said delay regulators includes means for providing its electrical manifestation in the form of a voltage.
Claim 7
Dependent Claim
208 words
In an electronic system, said system including: N interconnected integrated circuit chips, where N is an integer positive number, each of said N interconnected integrated circuit chips containing a delay regulator means and at least first, second and third interconnect logic circuits, said logic circuits on each of said chips having a relatively unique speed/power characteristic; a source of periodic clock pulses; said delay regulator means of each of said N interconnected circuit chips being adapted to receive said period clock pulses, each of said delay regulator means including active circuit means for generating an electrical manifestation related to said periodicity of said periodic clock pulses and said speed power characteristic of the logic circuits on the chip on which it is contained; and connection means on each of said N interconnected integrated circuit chips, said connection means on each of said N interconnected integrated circuit chips conveying the electrical manifestation generated by the delay regulator means on said chip to said logic circuits on said same chip, whereby the power provided to said logic circuits on said chips may vary chip to chip but said speed of said logic circuits on each of said chips will be essentially equal one to another and to the desired speed.
Claim 8
Dependent Claim
208 words
In an electronic system, said system including: N interconnected integrated circuit chips, where N is an integer positive number, each of said N interconnected integrated circuit chips containing a delay regulator means and at least first, second and third interconnect logic circuits, said logic circuits on each of said chips having a relatively unique speed/power characteristic; a source of periodic clock pulses; said delay regulator means of each of said N interconnected circuit chips being adapted to receive said period clock pulses, each of said delay regulator means including active circuit means for generating an electrical manifestation related to said periodicity of said periodic clock pulses and said speed power characteristic of the logic circuits on the chip on which it is contained; and connection means on each of said N interconnected integrated circuit chips, said connection means on each of said N interconnected integrated circuit chips conveying the electrical manifestation generated by the delay regulator means on said chip to said logic circuits on said same chip, whereby the power provided to said logic circuits on said chips may vary chip to chip but said speed of said logic circuits on each of said chips will be essentially equal one to another and to the desired speed.
Claim 9
Dependent Claim
22 words
In an electronic system, as recited in claim 6, wherein each of said delay regulator means essentially consists of a phase-locked loop.
Claim 10
Dependent Claim
59 words
In an electronic system, as recited in claim 6, wherein each of said delay regulator means of each of said N integrated circuit chips includes means for generating an on chip signal, each of said on chip generated signal of said N chips bearing a detectable relationship to the speed/power characteristics of the logic circuits on said same chip.
Claim 11
Dependent Claim
43 words
In an electronic system, as recited in claim 8, wherein each of said on chip generated signals of said N chips is a periodic pulse train and each of said detectable relationships is the periodicity of the on chip generated periodic pulse train.
Claim 12
Dependent Claim
24 words
In an electronic system, as recited in claim 6, wherein said generated electrical manifestation of each said delay regulator means is an electrical potential.
Claim 13
Dependent Claim
35 words
In an electronic system, as recited in claim 10, wherein each of said first, second and third interconnected logic circuits of each of said N interconnected integrated circuit chips is a current switch logic circuit.
Claim 14
Dependent Claim
135 words
In an electronic system, as recited in claim 6, wherein each of said delay regulator means comprises: a phase comparator circuit having first and second inputs and an output, said first input of said phase comparator circuit being adapted to receive said periodic clock pulses; a low pass filter circuit having an input connected to said output of said phase comparator and an output; a buffer circuit (or power amplifier) having an input connected to said output of said low pass filter circuit and an output; a voltage controlled oscillator means having an input connected to said output of said buffer circuit and an output; and a level shift circuit having an input connected to said output of said voltage controlled oscillator and an input connected to said second input of said phase comparator circuit.
Claim 15
Dependent Claim
55 words
In an electronic system, as recited in claim 12, wherein each of said first, second and third interconnected logic circuits have a speed/power characteristic which is directly electrically controllable by an electrical potential and wherein each of said electrical manifestations generated by the delay regulator means on each of said chips is an electrical potential.
Claim 16
Dependent Claim
86 words
In an electronic system, as recited in claim 12, wherein said voltage controlled oscillator means of each said delay regulator means comprises a recirculating loop frequency (RLF) means consisting essentially of a plurality of binary circuits each having an input and an output and serially connected in an enclosed loop with each binary circuit having its input connected to the output of a predetermined one of said plurality of binary circuits and its output connected to the input of another predetermined one of said binary circuits.
Claim 17
Dependent Claim
23 words
In an electronic system, as recited in claim 14, wherein said plurality of binary circuits includes an odd integer number of inverter circuits.
Claim 18
Dependent Claim
215 words
In an electronic system, said system comprising: at least first and second integrated circuit chips, said first chip containing at least first and second circuits, said first and second circuits of said first chip each having a gate delay versus power characteristic which is essentially identical one to the other, said second chip containing at least third and fourth circuits, said third and fourth circuits of said second chip each having a gate delay versus power characteristic which is essentially identical one to the other, a first delay regulator means contained on said first chip, said first delay regulator means being connected to said first and second circuits of said first chip, said first delay regulator means cooperating with a first periodic pulse source and said first and second circuits of said first chip to cause said first and second circuits to each have the same relatively constant gate delay, a second delay regulator means contained on said second chip, said second delay regulator means being connected to said third and fourth circuits of said second chip, said second delay regulator means cooperating with a second periodic pulse source and said third and fourth circuits of said second chip to cause said third and fourth circuits to each have the same relatively constant gate delay.
Claim 19
Dependent Claim
215 words
In an electronic system, said system comprising: at least first and second integrated circuit chips, said first chip containing at least first and second circuits, said first and second circuits of said first chip each having a gate delay versus power characteristic which is essentially identical one to the other, said second chip containing at least third and fourth circuits, said third and fourth circuits of said second chip each having a gate delay versus power characteristic which is essentially identical one to the other, a first delay regulator means contained on said first chip, said first delay regulator means being connected to said first and second circuits of said first chip, said first delay regulator means cooperating with a first periodic pulse source and said first and second circuits of said first chip to cause said first and second circuits to each have the same relatively constant gate delay, a second delay regulator means contained on said second chip, said second delay regulator means being connected to said third and fourth circuits of said second chip, said second delay regulator means cooperating with a second periodic pulse source and said third and fourth circuits of said second chip to cause said third and fourth circuits to each have the same relatively constant gate delay.
Claim 20
Dependent Claim
87 words
In an electronic system, as recited in claim 16, wherein said first delay regulator means and said second delay regulator means are logically equivalent one to the other, wherein said first periodic pulse source and said second periodic pulse source are provided by a single periodic pulse source having a relatively invariant pulse repetition rate, and wherein said first and second circuits of said first chip and said third and fourth circuits of said second chip are each of the same technological family such as current switch.
Claim 21
Dependent Claim
118 words
In an electronic system, as recited in claim 16, wherein said first delay regulator means and said second delay regulator means are logically similar one to the other, wherein said first periodic pulse source provides a first pulse train having a first pulse repetition rate, said second periodic pulse train provides a second pulse train having a second pulse repetition rate said first and second pulse repetition rates being unequal one to the other, wherein said first and second circuits of said first chip are respectively members of the current switch technological family and said third and fourth circuits of said second chip are respectively members of a like technological family other than said current switch technological family.
Claim 22
Dependent Claim
162 words
In an electronic system, said system comprising: at least a first integrated circuit chip said first integrated circuit chip containing at least first, second, third and fourth circuits, said first and second circuits each having a gate delay versus power characteristic which is essentially identical one to the other, said third and fourth circuits each having a gate delay versus power characteristic which is essentially identical one to the other, a first delay regulator means contained on said first chip, said first delay regulator means being connected to said first and second circuits, said first delay regulator means responding to a first periodic pulse train to cause said first and second circuits to each have the same relatively constant gate delay, said second delay regulator means being connected to said third and fourth circuits, said second delay regulator means responding to a second periodic pulse train to cause said third and fourth circuits to each have the same relatively constant gate delay.
Claim 23
Dependent Claim
162 words
In an electronic system, said system comprising: at least a first integrated circuit chip said first integrated circuit chip containing at least first, second, third and fourth circuits, said first and second circuits each having a gate delay versus power characteristic which is essentially identical one to the other, said third and fourth circuits each having a gate delay versus power characteristic which is essentially identical one to the other, a first delay regulator means contained on said first chip, said first delay regulator means being connected to said first and second circuits, said first delay regulator means responding to a first periodic pulse train to cause said first and second circuits to each have the same relatively constant gate delay, said second delay regulator means being connected to said third and fourth circuits, said second delay regulator means responding to a second periodic pulse train to cause said third and fourth circuits to each have the same relatively constant gate delay.
Claim 24
Dependent Claim
43 words
In an electronic system, as recited in claim 19, wherein said first and second circuits are respectively logical circuits of the current switch technological family and said third and fourth circuits are respectively logical circuits of a technology family other than current switch.
Claim 25
Dependent Claim
55 words
In an electronic system, as recited in claim 19, wherein the pulse repetition rate of said first pulse train is higher than the pulse repetition rated of said second pulse train whereby the gate delay of each of said first and second circuits is less than the gate delay of said third and fourth circuits.
Claim 26
Dependent Claim
197 words
An integrated circuit chip, said integrated circuit chip comprising: a plurality of logic circuits each having a gate delay versus power characteristic which is essentially identical one to the other; a delay regulator, said delay regulator being adapted to receive a clock pulse train, said delay regulator including a voltage controlled oscillator for providing an on chip generated periodic pulse train, said on chip generated periodic pulse train having a repetition rate related to said gate delay versus power characteristic of said plurality of logic circuits; comparison means contained within said delay regulator for comparing the phase relationship between said clock pulse train and said on chip generated periodic pulse train, said comparison means rendering an indication of the result of said comparison of the phase relationship between said clock pulse train and said on chip generated periodic pulse train; and circuit means connected between said comparison means of said delay regulator and each of said plurality of logic circuits for utilizing said indication of the phase relationship between said clock pulse train and said on chip generated periodic pulse train to regulate the gate delay of each of said plurality of logic circuits on said chip.
Claim 27
Dependent Claim
197 words
An integrated circuit chip, said integrated circuit chip comprising: a plurality of logic circuits each having a gate delay versus power characteristic which is essentially identical one to the other; a delay regulator, said delay regulator being adapted to receive a clock pulse train, said delay regulator including a voltage controlled oscillator for providing an on chip generated periodic pulse train, said on chip generated periodic pulse train having a repetition rate related to said gate delay versus power characteristic of said plurality of logic circuits; comparison means contained within said delay regulator for comparing the phase relationship between said clock pulse train and said on chip generated periodic pulse train, said comparison means rendering an indication of the result of said comparison of the phase relationship between said clock pulse train and said on chip generated periodic pulse train; and circuit means connected between said comparison means of said delay regulator and each of said plurality of logic circuits for utilizing said indication of the phase relationship between said clock pulse train and said on chip generated periodic pulse train to regulate the gate delay of each of said plurality of logic circuits on said chip.
Claim 28
Dependent Claim
97 words
In an electronic system including one or more interconnected integrated circuit chips, each of said one or more integrated circuit chips having a plurality of interconnected circuits thereon, each of said circuits having a delay versus power curve, said system being characterized by the inclusion of power control means for regulating the power to each of said circuits on each of said one or more chips whereby the delay of each of said interconnected circuits on each of said one or more interconnected integrated circuit chips is rendered essentially equal one to another and the desired delay.
Claim 29
Dependent Claim
97 words
In an electronic system including one or more interconnected integrated circuit chips, each of said one or more integrated circuit chips having a plurality of interconnected circuits thereon, each of said circuits having a delay versus power curve, said system being characterized by the inclusion of power control means for regulating the power to each of said circuits on each of said one or more chips whereby the delay of each of said interconnected circuits on each of said one or more interconnected integrated circuit chips is rendered essentially equal one to another and the desired delay.
Claim 30
Dependent Claim
27 words
In an electronic system, as recited in claim 23, wherein said plurality of interconnected circuits are respectively members of the T 2 L technological family of circuits.
Claim 31
Dependent Claim
27 words
In an electronic system, as recited in claim 23, wherein said plurality of interconnected circuits are respectively members of the I 2 L technological family of circuits.
Claim 32
Dependent Claim
25 words
In an electronic system, as recited in claim 23, wherein said plurality of interconnected circuits are respectively members of the ECL technological family of circuits.
Claim 33
Dependent Claim
19 words
In an electronic system, as recited in claim 23, wherein said plurality of interconnected circuits are F.E.T. type circuits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-08-23 | 1986-02-22 | 1986-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-08-23 | 1990-02-22 | 1990-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-08-23 | 1994-02-22 | 1994-08-24 | $7700.00 | Window Closed / Lapsed |