Compound semiconductor integrated circuit device

Claim 2

A compound semiconductor integrated circuit device including a bipolar transistor and a field effect transistor (FET), comprising: a semi-insulating substrate having first and second areas, said bipolar transistor being over the first area and said FET being over the second area; means for electrically isolating said bipolar transistor over the first area, from said FET over the second area; a first compound semiconductor layer of a first conductivity on said semi-insulating substrate; a second compound semiconductor layer of a second conductivity on said first compound semiconductor layer; and a third compound semiconductor layer of the first conductivity on said second compound semiconductor layer, at least one of said first and third compound semiconductor layers having a forbidden energy band gap larger than that of said second compound semiconductor layer; an electrode formed over said first compound semiconductor layer; said bipolar transistor comprising a base region of a part of said second compound semiconductor layer, an emitter region of a part of one of the at least one of said first and third compound semiconductor layers having a forbidden energy band gap larger than that of said second compound semiconductor layer, a collector region of a part of the other of the at least one of said first and third compound semiconductor layers, and said electrode over said first compound semiconductor layer; said FET comprising a channel region, a part of one of the first, second, and third compound semiconductor layers forming one of the channel region and a region for supplying electrons to the channel region.

Claim 3

A device according to claim 1, wherein: said first conductivity is n-type; said second conductivity is p-type; and said third compound semiconductor layer of n-type in the second area is the channel region of said FET.

Claim 4

A device according to claim 2, wherein said first compound semiconductor layer is Al x Ga 1-x As and said second and third compound semiconductor layers are GaAs.

Claim 5

A device according to claim 2, wherein said first compound semiconductor layers is Ga x In 1-x P y As 1-y and said second and third compound semiconductor layers are InP.

Claim 6

A device according to claim 2, wherein said first compound semiconductor layer is Ga x In 1-x P y As 1-y and said second and third compound semiconductor layers are Al x In 1-x As.

Claim 7

A device according to claim 1, wherein: said first conductivity is p-type; said second conductivity is n-type; and said second compound semiconductor layer of n-type in the second area is the channel region of said FET.

Claim 8

A device according to claim 6, further comprising a gate electrode on said third compound semiconductor layer in said second area, so that said FET is a junction-type FET.

Claim 9

A device according to claim 6, wherein said third compound semiconductor layer does not exist in the second area, said device further comprising a gate electrode on said second compound semiconductor layer in said second area, so that said FET is a metal-semiconductor FET.

Claim 10

A device according to claim 6, wherein said first and third compound semiconductor layers are Al x Ga 1-x As and said second compound semiconductor layer is GaAs.

Claim 11

A device according to claim 6, wherein said first and third compound semiconductor layers are InP and said second compound semiconductor layer is Ga x In 1-x P y As 1-y .

Claim 12

A device according to claim 6, wherein said first and third compound semiconductor layers are In x Ga 1-x As and said second compound semiconductor layer is Ga x In 1-x P y As 1-y .

Claim 13

A device according to claim 1, further comprising a fourth compound semiconductor layer under and adjacent to said first compound semiconductor layer in said first and second areas of said semi-insulating substrate, wherein said fourth compound semiconductor layer has an electron affinity larger than that of said first compound semiconductor layer, wherein said first conductivity is n-type, wherein said second conductivity is p-type, wherein a two-dimensional electron gas is formed of electrons transmitted from said first compound semiconductor layer to said fourth compound semiconductor layer, and wherein said two-dimensional electron gas is the channel region of said FET.

Claim 14

A device according to claim 12, wherein: said first compound semiconductor layer is Al x Ga 1-x As: said second, third, and fourth compound semiconductor layers are GaAs; and said fourth compound semiconductor layer of GaAs is undoped.

Claim 15

A device according to claim 12, wherein: said first compound semiconductor layer is InP; said second, third, and fourth compound semiconductor layers are Ga x In 1-x P y As 1-y ; and said fourth compound semiconductor layer of Ga x In 1-x P y As 1-y is undoped.

Claim 16

A device according to claim 12, wherein: said first compound semiconductor layer is Al x In 1-x As; said second, third, and fourth compound semiconductor layers are Ga x In 1-x P y As 1-y ; and said fourth compound semiconductor layer of Ga x In 1- P y As 1-y is undoped.

Claim 17

A compound semiconductor integrated circuit device including a bipolar transistor and a field effect transistor, comprising: a semi-insulating substrate having first and second areas, the bipolar transistor being formed over the first area and the field effect transistor being formed over the second area; means for electrically isolating the bipolar transistor formed over the first area from the field effect transistor formed over the second area; a first compound semiconductor layer of a first conductivity type formed over the first and second areas of said semi-insulating substrate; a second compound semiconductor layer of a second conductivity type formed on said first compound semiconductor layer over the first and second areas of said semi-insulating substrate; and a third compound semiconductor layer of the first conductivity type formed on said second compound semiconductor layer over at least the first area of said semi-insulating substrate, at least one of said first and third compound semiconductor layers being a forbidden energy band gap greater than the forbidden energy band gap of said second compound semiconductor layer; the bipolar transistor comprising the portions of said first, second and third compound semiconductor layers, which are over the first area of said semi-insulating substrate; the field effect transistor comprising the portions of said first and second compound semiconductor layers, which are over the second area of said semi-insulating substrate.

Claim 18

A compound semiconductor integrated circuit device including a bipolar transistor and a field effect transistor, comprising: a semi-insulating substrate having first and second areas, the bipolar transistor being formed over the first area and the field effect transistor being formed over the second area; means for electrically isolating the bipolar transistor formed over the first area from the field effect transistor formed over the second area; a first compound semiconductor layer of a first conductivity type formed over the first and second areas of said semi-insulating substrate; a second compound semiconductor layer of a second conductivity type formed on said first compound semiconductor layer over the first and second areas of said semi-insulating substrate; and a third compound semiconductor layer of the first conductivity type formed on said second compound semiconductor layer over at least the first area of said semi-insulating substrate, at least one of said first and third compound semiconductor layers being a forbidden energy band gap greater than the forbidden energy band gap of said second compound semiconductor layer; the bipolar transistor comprising the portions of said first, second and third compound semiconductor layers, which are over the first area of said semi-insulating substrate; the field effect transistor comprising the portions of said first and second compound semiconductor layers, which are over the second area of said semi-insulating substrate.

Claim 19

A device according to claim 16, further comprising a gate electrode formed on said second compound semiconductor layer over the second area of said semi-insulating substrate, so that said field effect transistor is a metal-semiconductor field effect transistor (MESFET).

Claim 20

A device according to claim 16, wherein: said third compound semiconductor layer is formed over the second area of said semi-insulating substrate; said first conductivity type is n-type; said second conductivity type is p-type; and said third compound semiconductor layer over the second area of said semi-insulating substrate is the channel region of said FET.

Claim 21

A device according to claim 18, wherein: said second compound semiconductor layer forms the base region of said bipolar transistor; and the one of said first and third compound semiconductor layers which has a forbidden energy band gap greater than that of said second compound semiconductor layers, forms the emitter of said bipolar transistor.

Claim 22

A compound semiconductor integrated circuit device including a bipolar transistor and a field effect transistor, comprising: a semi-insulating substrate having first and second areas, the bipolar transistor being formed over the first area and the field effect transistor being formed over the second area; means for electrically isolating the bipolar transistor formed over the first area from the field effect transistor formed over the second area; a first compound semiconductor layer formed over the first and second areas of said semi-insulating substrate; a second compound semiconductor layer formed on said first compound semiconductor layer over the first area of said semi-insulating substrate; a third compound semiconductor layer formed on said second compound semiconductor layer over the first area of said semi-insulating substrate; a fourth compound semiconductor layer formed over the first and second areas of said semi-insulating substrate between said semi-insulating substrate and said first compound semiconductor layer, said first compound semiconductor layer having a forbidden energy band gap greater than the forbidden energy band gap of said fourth compound semiconductor layer; the bipolar transistor comprising the portions of said first, second, third and fourth compound semiconductor layers which are over the first area of said semi-insulating substrate; the field effect transistor comprising the portions of said first and fourth compound semiconductor layers which are over the second area of said semi-insulating substrate, a two-dimensional electron gas being formed of electrons transmitted from said first compound semiconductor layer to said fourth compound semiconductor layer, said two-dimensional electron gas forming the channel region of said field effect transistor.

Claim 23

A compound semiconductor integrated circuit device including a bipolar transistor and a field effect transistor, comprising: a semi-insulating substrate having first and second areas, the bipolar transistor being formed over the first area and the field effect transistor being formed over the second area; means for electrically isolating the bipolar transistor formed over the first area from the field effect transistor formed over the second area; a first compound semiconductor layer formed over the first and second areas of said semi-insulating substrate; a second compound semiconductor layer formed on said first compound semiconductor layer over the first area of said semi-insulating substrate; a third compound semiconductor layer formed on said second compound semiconductor layer over the first area of said semi-insulating substrate; a fourth compound semiconductor layer formed over the first and second areas of said semi-insulating substrate between said semi-insulating substrate and said first compound semiconductor layer, said first compound semiconductor layer having a forbidden energy band gap greater than the forbidden energy band gap of said fourth compound semiconductor layer; the bipolar transistor comprising the portions of said first, second, third and fourth compound semiconductor layers which are over the first area of said semi-insulating substrate; the field effect transistor comprising the portions of said first and fourth compound semiconductor layers which are over the second area of said semi-insulating substrate, a two-dimensional electron gas being formed of electrons transmitted from said first compound semiconductor layer to said fourth compound semiconductor layer, said two-dimensional electron gas forming the channel region of said field effect transistor.