Integrated circuit device and process with tin-gate transistor

Claim 1

An integrated circuit device comprising: a substrate, including device isolation regions defining a plurality of moat area of exposed semiconducting material at a surface thereof; a first insulated-gate field effect transistor formed in a first moat area and having a portion of a first patterned conductive layer comprising polycrystalline silicon as a gate, and having source/drain regions; a connection formed of a second patterned conductive layer comprising titanium nitride, in contact with a source/drain region of said first insulated-gate field effect transistor and in contact with a conductive layer in a second moat area; a second insulated-gate field effect transistor comprising: first and second source/drains separated by a channel in a third moat area, a first gate-edge extension comprising a portion of said first patterned conductive layer disposed over said channel area near said first source/drain, a gate formed of a portion of said second patterned thin film conductive layer disposed over said channel area and laterally separated from said first source/drain by said first gate-edge extension, wherein said first gate-edge extension is capacitively coupled to said gate, and wherein said first gate-edge extension is capacitively coupled to said first source/drain.