EEPROM cell with integral select transistor

Claim 1

A process for forming an electrically programmable and electrically erasable memory cell in a silicon body comprising the steps of: forming a first insulative layer on said body; defining at least a first edge of a first polysilicon gate member from a first polysilicon layer formed on said first insulative layer; depositing a second insulative layer so as to cover said exposed portions of said first insulative layer and said first gate member; etching said second insulative layer so as to define a spacer member adjacent to said first edge of said first gate member; doping said silicon body with a first doping step with a dopant of a first conductivity type, said spacer member protecting a first region in said body under said spacer member from receiving said dopant; removing said spacer member; doping main body with a second doping step with a dopant of a second conductivity type so as to dope said first region with said dopant of said second conductivity type; forming a second polysilicon layer over said first gate member and insulated therefrom and defining a second gate member from said second layer, said second layer member extending over said first region; forming source and drain regions in said body with a third doping step in alignment with said second gate member; whereby a memory cell having an integrally formed select device is realized.