Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
460 words
A secondary storage system for a data processing system, said secondary storage system comprising a mass storage device, a controller for effectuating operations of the device, and an apparatus for establishing a communications path between the controller and device, said apparatus for establishing a communications path being capable of communicating command, response, data and status information on only four unidirectional channels, whereas similar information is normally communicated between a device and controller on more than four unidirectional channels by a standard apparatus for establishing a communication path, said apparatus comprising: a radial bus, comprising substantially only first and second unidirectional channels for carrying signals from said controller to said device and third and fourth unidirectional channels for carrying signals from said device to said controller; means associated with the controller for generating and applying to the first channel and means associated with the device for receiving from the first channel, a continuous transmission of sequences of bit-multiplexed, bit-serial, real-time, signals, each of said sequences being indicative of a set of status variables that define the state of the controller; means associated with the controller for generating and applying to the second channel and means associated with the device for receiving from the second channel, bit-serial command messages and write data; means associated with the device for generating and applying to the third channel and means associated with the controller for receiving from the third channel, a continuous transmission of sequences of bit-multiplexed, bit-serial, real-time signals, each of said sequences being indicative of a set of status variables that define the state of the device; means associated with the device for generating and applying to the fourth channel and means associated with the controller for receiving from the fourth channel, bit-serial response messages and read data; means associated with the controller, responsive to said sequences of signals indicative of a set of status variables of the device an responsive to said response messages and read data, for effectuating the operation of said controller; means associated with the device, responsive to said sequence of signals indicative of a set of status variables of the controller and responsive to said command messages and write data, for effectuating the operation of said device; and wherein each of said sequence indicative of the state of the mass storage device is a bit pattern and wherein within said bit pattern indicative of the state of the device, A. a predetermined first bit provides a synchronization bit; B. a predetermined second bit provides a receiver ready signal; C. a predetermined third bit provides an attention signal; D. a predetermined fourth bit provides a read/write ready signal; E. a predetermined fifth bit provides a sector pulse signal; and F. a predetermined sixth bit provides an available status signal.
Claim 2
Dependent Claim
460 words
A secondary storage system for a data processing system, said secondary storage system comprising a mass storage device, a controller for effectuating operations of the device, and an apparatus for establishing a communications path between the controller and device, said apparatus for establishing a communications path being capable of communicating command, response, data and status information on only four unidirectional channels, whereas similar information is normally communicated between a device and controller on more than four unidirectional channels by a standard apparatus for establishing a communication path, said apparatus comprising: a radial bus, comprising substantially only first and second unidirectional channels for carrying signals from said controller to said device and third and fourth unidirectional channels for carrying signals from said device to said controller; means associated with the controller for generating and applying to the first channel and means associated with the device for receiving from the first channel, a continuous transmission of sequences of bit-multiplexed, bit-serial, real-time, signals, each of said sequences being indicative of a set of status variables that define the state of the controller; means associated with the controller for generating and applying to the second channel and means associated with the device for receiving from the second channel, bit-serial command messages and write data; means associated with the device for generating and applying to the third channel and means associated with the controller for receiving from the third channel, a continuous transmission of sequences of bit-multiplexed, bit-serial, real-time signals, each of said sequences being indicative of a set of status variables that define the state of the device; means associated with the device for generating and applying to the fourth channel and means associated with the controller for receiving from the fourth channel, bit-serial response messages and read data; means associated with the controller, responsive to said sequences of signals indicative of a set of status variables of the device an responsive to said response messages and read data, for effectuating the operation of said controller; means associated with the device, responsive to said sequence of signals indicative of a set of status variables of the controller and responsive to said command messages and write data, for effectuating the operation of said device; and wherein each of said sequence indicative of the state of the mass storage device is a bit pattern and wherein within said bit pattern indicative of the state of the device, A. a predetermined first bit provides a synchronization bit; B. a predetermined second bit provides a receiver ready signal; C. a predetermined third bit provides an attention signal; D. a predetermined fourth bit provides a read/write ready signal; E. a predetermined fifth bit provides a sector pulse signal; and F. a predetermined sixth bit provides an available status signal.
Claim 3
Dependent Claim
25 words
The apparatus of claim 1 wherein each of said sequences indicative of the state of the controller is a bit pattern of a predetermined length.
Claim 4
Dependent Claim
66 words
The apparatus of claim 2 wherein within bit said pattern indicative of the state of the controller A. a predetermined first bit provides a synchronization bit; B. a predetermined second bit provides a receiver ready signal; C. a predetermined third bit provides a write gate signal; D. a predetermined fourth bit provides a read gate signal; and E. a predetermined fifth bit provides an initialization signal.
Claim 5
Dependent Claim
21 words
The apparatus of claim 3 wherein said pattern further includes F. a predetermined sixth bit which serves as a parity bit.
Claim 6
Dependent Claim
25 words
The apparatus of claim 4 wherein said pattern further includes a plurality of bits of predetermined value comprising a preamble which preceeds said first bit.
Claim 7
Dependent Claim
16 words
The apparatus of claim 5 wherein the preamble comprises a predetermined number of a zero-valued bits.
Claim 8
Dependent Claim
40 words
The apparatus of claim 1 wherein said bit pattern indicative of the state of the device includes G. a predetermined seventh bit which serves as index pulse signal; and H. a predetermined eighth bit which serves as a parity bit.
Claim 9
Dependent Claim
25 words
The apparatus of claim 7 wherein said pattern further includes a plurality of bits of predetermined value comprising a preamble which preceeds said first bit.