Alternating data buffers when one buffer is empty and another buffer is variably full of data

Claim 2

In a data path concentrator for connecting a high speed unit to a plurality of signal burst units for transferring signals in bursts of such signals therebetween, the improvement comprising: a plurality of electrical signal burst accommodating means respectively for connecting said signal burst units to said high speed unit; each said accommodating means comprising a plurality of switchable buffer means for receiving and temporarily storing signals being transferred and having control means responsive to a one of said buffer means therein which is receiving signals which partially fill such receiving means to a given intermediate filled state buffer to switch signals being received from said one of said buffer means to another of said buffer means in such accommodation means whenever said another buffer means is empty and means responsive to the predetermined data activities of all of said units for selectively activating said accommodating means to buffer bursts of signals, whereby all said signal burst accommodating means may simultaneously receive signals for transfer between said high speed unit and respective ones of said signal burst means at maximal data transfer rates.

Claim 3

The concentrator set forth in claim 1 wherein in each of said accommodating means each said buffer includes empty indicating means for indicating no signals being stored in a respective buffer means, and each said control means of each said accommodating means being jointly responsive to said given intermediate filled state and to an empty indicating means in such accommodating means to switch said signals being received thereby to another of said buffer means therein, respectively.

Claim 4

In a buffered signal exchange apparatus for being coupled to a data signal receiving apparatus to receive data signals supplied by the buffer signal exchange apparatus, comprising in combination: a plurality of buffer register sets, each of said buffer register sets having a given number of addressable registers to store signals being buffered and a ready means indicating data signals being received have filled a predetermined number of said addressable registers which predetermined number is less than said given number; signal means connected to all said sets for supplying data signals thereto for buffering and connected to said sets for transfer to said data signal receiving apparatus by supplying buffered data signals thereto; control means connected to said sets for indicating that a given one of said sets is receiving signals to be buffered; means connected to all said buffer register sets for being responsive to all said ready means except said ready means in said given one set and to said control means indicating said given one said set is receiving signals to electrically indicate that a said set other than said given one set is to receive signals to be buffered irrespective of whether or not said given one set has received said signals to be buffered up to said given number of registers; and electronic switch means electrically interposed between all said sets and said signal means and being responsive to said responsive means said electrical indication to connect said register sets and said signal means in accordance with said responsive means indication whereby a maximal data transfer bandwidth is provided by said buffer register sets for data signals being transferred therethrough.

Claim 5

In a buffered signal exchange apparatus for being coupled to a data signal receiving apparatus to receive data signals supplied by the buffer signal exchange apparatus, comprising in combination: a plurality of buffer register sets, each of said buffer register sets having a given number of addressable registers to store signals being buffered and a ready means indicating data signals being received have filled a predetermined number of said addressable registers which predetermined number is less than said given number; signal means connected to all said sets for supplying data signals thereto for buffering and connected to said sets for transfer to said data signal receiving apparatus by supplying buffered data signals thereto; control means connected to said sets for indicating that a given one of said sets is receiving signals to be buffered; means connected to all said buffer register sets for being responsive to all said ready means except said ready means in said given one set and to said control means indicating said given one said set is receiving signals to electrically indicate that a said set other than said given one set is to receive signals to be buffered irrespective of whether or not said given one set has received said signals to be buffered up to said given number of registers; and electronic switch means electrically interposed between all said sets and said signal means and being responsive to said responsive means said electrical indication to connect said register sets and said signal means in accordance with said responsive means indication whereby a maximal data transfer bandwidth is provided by said buffer register sets for data signals being transferred therethrough.

Claim 6

The apparatus set forth in claim 3 further including empty indicating means to electrically indicate when a one of said buffer register sets supplying data signals is empty of said data signals being supplied and said responsive means being jointly responsive to a said ready means and said empty indicating means respective indications of said predetermined number of said addressable registers being filled with data signals received to be buffered and if said one buffer register set supplying data signals is empty of said data signals being supplied to indicate said one of said buffer register sets supplying data signals is to receive signals instead of said given buffer register set.

Claim 7

The apparatus set forth in claim 4 wherein each said ready means indicates said number of registers as a number which is submultiple of said given number for the respective buffer register sets.

Claim 8

The apparatus set forth in claim 5 wherein each said ready means includes means to select said indicated number of registers.

Claim 9

The apparatus set forth in claim 6 wherein each of said plurality of buffer register sets includes means for receiving a unit size of data transfer such that said indicated number of registers is derived from a data transfer unit size to be used with said respective buffer register set.

Claim 10

In alternating data buffer apparatus having first and second register sets, switch means connected to said register sets for switching access thereto for respectively receiving or delivering data signals, each register set having a predetermined number of addressable registers for storing data signals; the improvement including in combination: decoding means connected to said register sets for indicating when one of said register sets has data signals stored in any one of a plurality of a given numbers of said registers therein, said given number being less than or equal to said predetermined number, and for indicating when a second of said register sets has no data stored therein, said one register set receiving data signals; and control means connected to said decoding means and said switch means and being responsive to said indications to activate and said switch means to alternate access to said register sets such that said one register set now delivers stored data signals from said given number of registers whereby alteration between said first and second register sets access at a maximal frequency with successive alternations occurring at diverse ones of said given numbers.

Claim 11

In alternating data buffer apparatus having first and second register sets, switch means connected to said register sets for switching access thereto for respectively receiving or delivering data signals, each register set having a predetermined number of addressable registers for storing data signals; the improvement including in combination: decoding means connected to said register sets for indicating when one of said register sets has data signals stored in any one of a plurality of a given numbers of said registers therein, said given number being less than or equal to said predetermined number, and for indicating when a second of said register sets has no data stored therein, said one register set receiving data signals; and control means connected to said decoding means and said switch means and being responsive to said indications to activate and said switch means to alternate access to said register sets such that said one register set now delivers stored data signals from said given number of registers whereby alteration between said first and second register sets access at a maximal frequency with successive alternations occurring at diverse ones of said given numbers.

Claim 12

The apparatus set forth in claim 8 further including program means in said decoding means for selectively controlling operation thereof.

Claim 13

The apparatus set forth in claim 9 further including address means indicating write and read addresses in each said register sets, and compare means in each said decoding means respectively connected to said address means for generating said indications of said given number and no data stored.

Claim 14

The apparatus set forth in claim 10 wherein said compare means includes address look ahead means for indicating said given number and no data stored before a data transfer operation.

Claim 15

The apparatus set forth in claim 8 further including: data means for initiating a data operation with respect to said register sets and for resetting said decoding means indications upon initiation of such data data operation.

Claim 16

The apparatus set forth in claim 8 further including means detecting a data full state in one of said register sets and inhibiting further data operations of receiving data signals by said one register set and said decoding means having memory means maintaining said given number indication for said one register set at least until a second one of said register sets has no data.

Claim 17

In an alternating data buffer apparatus having first and second register sets, each set having a predetermined number of addressable registers, and switch means for alternatively accessing said register sets for receiving and delivering data signals, the improvement including in combination: first and second addressing means respectively indicating which registers of said first and second register sets, respectively, contain data signals in said register sets; first and second ready means responsive to said first and second addressing means indications of which registers of said first and second register sets contain data signals, respectively, for indicating that said register sets have a given number of registers containing data signals, said given number being an integral submultiple, including unity, of a whole number less than a number of registers in said register sets; and control means responsive to either of said ready means indicating that said register sets have a given number of registers containing data signals to actuate said switch means to alternate access to said register sets whereby alternations between said first and second register sets can occur at a frequency greater than if a register set receiving data signals to be buffered were filled with said data signals being received by said register set receiving data signals before such alternation occurs.

Claim 18

In an alternating data buffer apparatus having first and second register sets, each set having a predetermined number of addressable registers, and switch means for alternatively accessing said register sets for receiving and delivering data signals, the improvement including in combination: first and second addressing means respectively indicating which registers of said first and second register sets, respectively, contain data signals in said register sets; first and second ready means responsive to said first and second addressing means indications of which registers of said first and second register sets contain data signals, respectively, for indicating that said register sets have a given number of registers containing data signals, said given number being an integral submultiple, including unity, of a whole number less than a number of registers in said register sets; and control means responsive to either of said ready means indicating that said register sets have a given number of registers containing data signals to actuate said switch means to alternate access to said register sets whereby alternations between said first and second register sets can occur at a frequency greater than if a register set receiving data signals to be buffered were filled with said data signals being received by said register set receiving data signals before such alternation occurs.

Claim 19

The apparatus set forth in claim 14 wherein each said addressing means has a write counter for indicating a register address of a register for receiving data signals, and a read counter for indicating a register address of a register for supplying data signals.

Claim 20

The apparatus set forth in claim 15 wherein each said ready means includes a compare means connected to a respective one of said write counters and each said compare means being respectively responsive to said write counters signal contents to supply said given number indication.

Claim 21

The apparatus set forth in claim 16 wherein each said compare means includes an AND circuit connected to predetermined portions of said respective write counters and said predetermined portions respectively having a count value equal to said given number.

Claim 22

The apparatus set forth in claim 15 further including first and second compare means connected to said write counter and said read "counter," respectively, of said first and second addressing means, each said compare means being responsive to said write counter and said read counter in said respective addressing means to supply a respective first and second switch controlling signal to said control means, and said control means being responsive to said given number indication only when receiving one of said switch controlling signals.

Claim 23

The apparatus set forth in claim 18 wherein each said compare means includes an add one circuit means for adjusting the signal contents received from said respective read counter for supplying said switch controlling signal before ensuing data operation.

Claim 24

The machine-implemented method of operating a data memory having a predetermined number of addressable registers, comprising the automatic machine-executable steps of: dividing said registers into two groups of registers, writing data signals received from a data signal sourcing apparatus while reading data signals from a second group of said registers, and transferring said read data signals to a data signal receiving apparatus, sensing when data signals being read from said second group have been completely read out, dividing each said group of registers into a plurality of blocks of registers, sensing when said one group of registers has received data signals filling any integral number of said blocks of registers, and when data signals being read from said second group of registers have been completely read out and said one group of registers has any number of blocks filled with said data signals being written, switching accessing of said groups such that said one group of registers is to be read from while said second group of registers is to be written into.

Claim 25

The machine-implemented method of operating a data memory having a predetermined number of addressable registers, comprising the automatic machine-executable steps of: dividing said registers into two groups of registers, writing data signals received from a data signal sourcing apparatus while reading data signals from a second group of said registers, and transferring said read data signals to a data signal receiving apparatus, sensing when data signals being read from said second group have been completely read out, dividing each said group of registers into a plurality of blocks of registers, sensing when said one group of registers has received data signals filling any integral number of said blocks of registers, and when data signals being read from said second group of registers have been completely read out and said one group of registers has any number of blocks filled with said data signals being written, switching accessing of said groups such that said one group of registers is to be read from while said second group of registers is to be written into.

Claim 26

The machine-implemented method set forth in claim 20 further including the automatic machine-executable steps of selecting a number of registers for each block of registers in accordance with a number of data signals to be transferred as a minimal number of data signals.