US4087626A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Scrambler and unscrambler for serial data
Assignee: RCA Corp
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Filing: 1976-08-04
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Granted: 1978-05-02
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Expires: 1996-08-04
Abstract
Abstract Serial data is scrambled at a transmitting terminal by storing it in sequential locations in a first random access memory, while previously stored information is read out of a second random access memory using a pseudo-random address counter. Whenever one memory is filled and the other memory is emptied, the roles of the memories are transposed. Similar apparatus at a receiving terminal is operated in synchronism and phase to unscramble the received data.
Inventors
- 👤 Roy Henry Brader
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 15:34
CPC Classifications
H; H04; H04L; H04L9/00; H04L9/34; H04L25/00; H04L25/02; H04L25/05; H04L9/06; H04L9/065; H04L9/0656; H04L9/12
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
81 words
A data reordering system, comprising first and second random access memories, a numerical memory address counter providing addresses in numerical sequence, a pseudo-random memory address counter providing addresses in a pseudo-random sequence, means to store serial data in said first memory in storage locations determined by one of said address counters while serially reading data out of said second memory from storage locations determined by the other of said address counters, and means periodically to transpose said first and second memories.
Claim 2
Dependent Claim
81 words
A data reordering system, comprising first and second random access memories, a numerical memory address counter providing addresses in numerical sequence, a pseudo-random memory address counter providing addresses in a pseudo-random sequence, means to store serial data in said first memory in storage locations determined by one of said address counters while serially reading data out of said second memory from storage locations determined by the other of said address counters, and means periodically to transpose said first and second memories.
Claim 3
Dependent Claim
26 words
A system as defined in claim 1 wherein said means to transpose said memories operates when one memory is filled and the other memory is emptied.
Claim 4
Dependent Claim
46 words
A system as defined in claim 1 wherein said means to store data in the first memory uses said numerical address counter while data is read out of said second memory using said pseudo-random address counter, whereby to scramble the serial data at a transmitting terminal.
Claim 5
Dependent Claim
45 words
A system as defined in claim 1 wherein said means to store data in the first memory uses said pseudo-random address counter while data is read out of said second memory using said numerical address counter, whereby to unscramble the data at a receiving terminal.
Claim 6
Dependent Claim
111 words
A data transmission system, comprising a serial data scrambler at a transmitting terminal and a serial data unscrambler at a receiving terminal, each including: two random access memories, a numerical memory address counter providing addresses in numerical sequence, a pseudo-random memory address counter providing addresses in a pseudo-random sequence, means to store serial data in one of said memories in storage locations determined by one of said address counters while serially reading data out of the other of said memories from storage locations determined by the other of said address counters, and means periodically to transpose the store and read-out operations of said memories using transposed ones of said address counters.
Claim 7
Dependent Claim
111 words
A data transmission system, comprising a serial data scrambler at a transmitting terminal and a serial data unscrambler at a receiving terminal, each including: two random access memories, a numerical memory address counter providing addresses in numerical sequence, a pseudo-random memory address counter providing addresses in a pseudo-random sequence, means to store serial data in one of said memories in storage locations determined by one of said address counters while serially reading data out of the other of said memories from storage locations determined by the other of said address counters, and means periodically to transpose the store and read-out operations of said memories using transposed ones of said address counters.
Claim 8
Dependent Claim
58 words
A system as defined in claim 5, and in addition a synchronizing and phasing means to cause the translation at the transmitting terminal of data in numerical sequence to data in pseudo-random sequence, at the same time that is causes the translation at the receiving terminal of data in said pseudo-random sequence to data in said numerical sequence.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-05-01 | 1981-10-31 | 1982-05-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-05-01 | 1985-10-31 | 1986-05-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-05-01 | 1989-10-31 | 1990-05-02 | $7700.00 | Window Closed / Lapsed |