Insulated gate device

Claim 2

A semiconductor device formed in and on a substrate having a major surface, said device comprising: a first region within said substrate of a first conductivity type, said first region having a first surface area adjacent said major surface; a second region within said substrate of a second conductivity type opposite of said first conductivity type, said second region bounding said first region within said substrate and having a second surface area adjacent said major surface; an insulating layer disposed over said first and second surface areas, said insulating layer including a contact window formed in said insulating layer over a first portion of said first surface area and a second portion of said second surface area which is adjacent to and extends along said first portion of the first surface area, the ratio of the area of said second portion to the area of said first portion being greater than or equal to one-third, and said contact window having at least part of its edge located over said second surface area; a first electrode layer disposed in said contact window and making ohmic contact with said first and second portions of said first and second regions respectively; and a gate electrode overlying a portion of said insulating layer.

Claim 3

The semiconductor device of claim 1 wherein said contact window is substantially rectangularly shaped and includes a pair of longitudinal sides and a pair of transverse ends, the ratio of the length of said sides to the length of said ends being greater than or equal to twenty.

Claim 4

The semiconductor device of claim 1 further comprising: a third region within said substrate of said first conductivity type adjacent said second region: a fourth region within said substrate of said second conductivity type in contact with said third region; a gate electrode disposed on said insulating layer and over a part of said second region which is between said first and third regions; and a second electrode layer making ohmic contact with said fourth region.

Claim 5

The semiconductor device of claim 3 wherein said first region, said second region, said insulating layer, said first electrode layer and said gate electrode comprise a first cell, said device further comprising one or more additional cells each substantially identical to said first cell and all having their first electrode layers connected together and their gate electrodes connected together.

Claim 6

A semiconductor device formed in and on a substrate having a major surface, said device comprising: a first region within said substrate of a first conductivity type, said first region having a first surface area adjacent said major surface; a second region within said substrate of a second conductivity type opposite of said first conductivity type, said second region bounding said first region within said substrate and having a second surface area adjacent said major surface; an insulating layer disposed over said first and second surface area, said insulating layer including a contact window formed in said insulating layer over a first portion of said first surface area and a second portion of said second surface area which is adjacent to and extends along said first portion of the first surface area, said second portion including sections of said second surface area which are spaced from the junction between said first and second regions so as to reduce crowding of current flowing in said second region to said contact window; a first electrode layer disposed in said contact window and making ohmic contact with said first and second portions of said first and second regions, respectively; and a gate electrode overlying a portion of said insulating layer.

Claim 7

A semiconductor device formed in and on a substrate having a major surface, said device comprising: a first region within said substrate of a first conductivity type, said first region having a first surface area adjacent said major surface; a second region within said substrate of a second conductivity type opposite of said first conductivity type, said second region bounding said first region within said substrate and having a second surface area adjacent said major surface; an insulating layer disposed over said first and second surface area, said insulating layer including a contact window formed in said insulating layer over a first portion of said first surface area and a second portion of said second surface area which is adjacent to and extends along said first portion of the first surface area, said second portion including sections of said second surface area which are spaced from the junction between said first and second regions so as to reduce crowding of current flowing in said second region to said contact window; a first electrode layer disposed in said contact window and making ohmic contact with said first and second portions of said first and second regions, respectively; and a gate electrode overlying a portion of said insulating layer.

Claim 8

The semiconductor device of claim 5 wherein said contact window is substantially rectangularly shaped and includes a pair of longitudinal sides and a pair of transverse ends, said second portion of said second surface area including a pair of end portions, each end portion being adjacent and coextensive with a respective transverse end of said contact window.

Claim 9

The semiconductor device of claim 6 wherein each of said end portions is substantially rectangular in shape.

Claim 10

The semiconductor device of claim 6 wherein said first portion of said first surface area includes a pair of side portions, each proximate to a respective longitudinal side of said contact window, and wherein said second portion of said second surface area further includes a center portion disposed between said pair of side portions of said first surface area.

Claim 11

The semiconductor device of claim 8 wherein said first portion of said first surface area includes at least one bridge portion interconnecting said side portions and interrupting said center portion.

Claim 12

The semiconductor device of claim 8 wherein said side portions are each comprised of a plurality of longitudinally spaced segments, and wherein said center portion includes lateral extensions between successive segments in each of said side portions.

Claim 13

The semiconductor device of claim 10 wherein said first portion of said first surface area further includes at least one bridge portion interconnecting a segment from one side portion with a respective segment from the other side portion.

Claim 14

The semiconductor device of claim 5 wherein the ratio of the area of said second portion to the area of said first portion is greater than or equal to one-third.

Claim 15

The semiconductor device of claim 5 further comprising: a third region within said substrate of said first conductivity type adjacent said second region: a fourth region within said substrate of said second conductivity type in association with said third region; a gate electrode disposed on said insulating layer and over a part of said second region which is between said first and third regions; and a second electrode layer making ohmic contact with said fourth region.

Claim 16

The semiconductor device of claim 13 wherein said first region, said second region, said insulating layer, said first electrode layer and said gate electrode comprise a first cell, said device further comprising one or more additional cells each substantially identical to said first cell and all having their first electrode layers connected together and their gate electrodes connected together.