Variable shift-count bidirectional shift control circuit

Claim 2

A shift control circuit comprising: (a) bit string generator means for producing a string of a predetermined number of data bits, (b) switching means for detecting the positive or negative sign of the bit string and producing a first switch signal responsive to the positive sign of the bit string or a second switch signal responsive to the negative sign of the bit string; (c) one's complement generator means for producing a signal representative of the one's complement of said bit string, (d) first selective signal transfer means responsive to said first and second switch signals for allowing said bit string to pass therethrough in response to the first switch signal or to the signal from said one's complement generator means in response to the second switch signal, (e) decoder means for decoding the bit string or the signal passed through said first selective signal transfer means for producing a decoded output signal, (f) single-bit shifting means for shifting the bit of the decoded output signal by a single-bit in a predetermined direction for producing a single-bit shifted output signal, and (g) second selective signal transfer means responsive to said first and second switch signals for allowing said decoded output signal to pass therethrough in response to said first switch signal or to the signal from said single-bit shifting means in response to said second switch signal.

Claim 3

A shift control circuit comprising: (a) bit string generator means for producing a string of a predetermined number of data bits, (b) switching means for detecting the positive or negative sign of the bit string and producing a first switch signal or a second switch signal responsive to the negative sign of the bit string, (c) first selective signal transfer means responsive to said first and second switch signals for allowing said bit string to pass therethrough in response to the first switch signal in response to the second switch signal, (d) one's complement generator means responsive to said first and second switch signals for producing a signal representative of the one's complement of said bit string in response to said second switch signal, (e) decoder means for decoding the bit string or the signal passed through said first selective signal transfer means for producing a decoded output signal, (f) single-bit shifting means for shifting the bit of the decoded output signal by a single bit in a predetermined direction for producing a single-bit shifted output signal, and (g) second selective signal transfer means responsive to said first and second switch signals for allowing said decoded output signal to pass therethrough in response to said first switch signal or to the signal from said single-bit shifting means in response to said second switch signal.

Claim 4

A shift control circuit comprising: (a) bit string generator means for producing a string of a predetermined number of data bits, (b) switching means for detecting the positive or negative sign of the bit string and producing a first switch signal or a second switch signal responsive to the negative sign of the bit string, (c) first selective signal transfer means responsive to said first and second switch signals for allowing said bit string to pass therethrough in response to the first switch signal in response to the second switch signal, (d) one's complement generator means responsive to said first and second switch signals for producing a signal representative of the one's complement of said bit string in response to said second switch signal, (e) decoder means for decoding the bit string or the signal passed through said first selective signal transfer means for producing a decoded output signal, (f) single-bit shifting means for shifting the bit of the decoded output signal by a single bit in a predetermined direction for producing a single-bit shifted output signal, and (g) second selective signal transfer means responsive to said first and second switch signals for allowing said decoded output signal to pass therethrough in response to said first switch signal or to the signal from said single-bit shifting means in response to said second switch signal.

Claim 5

A shift control circuit as set forth in claim 2, in which (h) said first selective transfer means comprises a plurality of first signal transmission gate means respectively responsive to the individual bits of the bit string produced by said bit string generator means, each of said first signal transmission gate means having a control terminal responsive to said first and second switch signals from said switch means and being activated to pass said bit string therethrough in response to the first switch signal, and (i) said ones complement generator means comprises a plurality of second signal transmission gate means respectively responsive to the individual bits of bit string produced by said bit string generator means, and a plurality of inverter means respectively connected to said second signal transmission gate means respectively operative to invert the individual bits of said bit string, each of said second signal transmission gate means having a control terminal responsive to said first and second switch signals from said switch means and being activated to pass therethrough the bits inverted by said inverters in response to said second switch signal.

Claim 6

A shift control circuit of a floating-point arithmetic system wherein a floating-point arithmetic routine is executed for two dyadic operands which consist of first and second number words each having an exponent part and a mantissa part, the shift control circuit comprising: (a) signal generating means for generating signals representative of the respective exponent parts and respective mantissa parts and of said first and second number words; (b) a first subtracter circuit responsive to the signals representative of the respective exponent parts and of said first and second number words and for subtracting the exponent part of said second number word from the exponent part of said first number word and producing a signal including a string of data bits indicative of the result of the arithmetic subtraction; (c) a logic circuit responsive to the signal from said first subtracter circuit for determining whether the result of said arithmetic subtraction has a negative sign with the exponent part larger than the exponent part and producing a signal of a predetermined logic state when it is determined that the result of the arithmetic subtraction has a negative sign: (d) a one's complement generator circuit responsive to the signal from said first subtracter circuit for generating a signal representative of the one's complement of said result of arithmetic subtraction; (e) a first multiplexer responsive to the signals from said subtractor circuit and said one's complement generator circuit and to the signal from said logic circuit, the first multiplexer having a first state allowing the signal from the one's complement generator circuit to pass therethrough and a second state allowing the signal from the subtractor circuit to pass therethrough, the first multiplexer having said first state in the absence of the signal of said predetermined logic state from said logic circuit and having said second state in the presence of the signal of said predetermined logic state from said logic circuit; (f) a decoder circuit for decoding the signal passed through said first multiplexer for producing a decoded output signal; (g) a single-bit shift circuit for shifting the bits of the decoded output signal by a single bit in a predetermined direction for producing a single-bit shifted output signal, (h) a second multiplexer responsive to the signals from said decoder circuit and said single-bit shift circuit and to the signal from said logic circuit, the second multiplexer having a first state allowing the signal from the decoder circuit to pass therethrough and a second state allowing the signal from the single-bit shift circuit to pass therethrough, the second multiplexer having said first state thereof in the absence of the signal of said predetermined logic state from said logic circuit and said second state thereof in the presence of the signal of said predetermined logic state from said logic circuit; (i) a third multiplexer responsive to the signal indicative of the exponent part of said first number word and the signal indicative of the exponent part of said second number word, and to the signal from said logic circuit, the third multiplexer having a first state allowing the signal indicative of the exponent part of said first number word to pass therethrough and a second state allowing the signal indicative of the exponent part of said second number word to pass therethrough, the third multiplexer having said first state thereof in the absence of the signal of the predetermined logic state from said logic circuit and said second state thereof in the presence of the signal of the predetermined logic state form said logic circuit, the signal indicative of the exponent part of said first number word being passed through the third multiplexer and output as representative of the exponent part of an output number word when the third multiplexer has said first state thereof and the signal indicative of the exponent part of the second number word being passed through the third multiplexer and is output as representative of the exponent part of said output number word when the third multiplexer has said second state thereof; (j) a fourth multiplexer responsive to the signal indicative of the mantissa part of said first number word and the signal indicative of the mantissa part of said second number word, and to the signal from said logic circuit, the fourth multiplexer having a first state allowing the signal indicative of the mantissa part of said first number word to pass therethrough and a second state allowing the signal indicative of the mantissa part of said second number word to pass therethrough, the fourth multiplexer having said first state thereof in the absence of the signal of the predetermined logic state from said logic circuit and said second state thereof in the presence of the signal of the predetermined logic state form said logic circuit; (k) a fifth multiplexer responsive to the signal indicative of the mantissa part of said first number word and the signal indicative of the mantissa part of said second number word, and to the signal from said logic circuit, the fifth multiplexer having a first state allowing the signal indicative of the mantissa part of said second number word to pass therethrough and a second state allowing the signal indicative of the mantissa part of said first number word to pass therethrough, the fifth multiplexer having said first state thereof in the absence of the signal of the predetermined logic state from said logic circuit and said second state thereof in the presence of the signal of the predetermined logic state from said logic circuit; (l) a right circuit responsive to the signals respectively passesd through said second and fifth multiplexers, and operative to make a rightward shift of the digits of the signal from the fourth multiplexer with a bit count represented by the signal from the second multiplexer for producing a signal representative of a right-shifted version of the mantissa part of said second number word; and (m) a dyadic arithmetic circuit having one input terminal responsive to the signal passed through said fourth multiplexer and another input terminal responsive to the signal output from arithmetic addition or subtraction between the input signal representative of the mantissa part of said first number word and the signal representative of the right-shifted version of the original mantissa part of said second number word, the signal resulting from said arithmetic addition or subtraction being output from the arithmetic circuit as being representative of the mantissa part of said output number word.

Claim 7

A shift control circuit of a floating-point arithmetic system wherein a floating-point arithmetic routine is executed for two dyadic operands which consist of first and second number words each having an exponent part and a mantissa part, the shift control circuit comprising: (a) signal generating means for generating signals representative of the respective exponent parts and respective mantissa parts and of said first and second number words; (b) a first subtracter circuit responsive to the signals representative of the respective exponent parts and of said first and second number words and for subtracting the exponent part of said second number word from the exponent part of said first number word and producing a signal including a string of data bits indicative of the result of the arithmetic subtraction; (c) a logic circuit responsive to the signal from said first subtracter circuit for determining whether the result of said arithmetic subtraction has a negative sign with the exponent part larger than the exponent part and producing a signal of a predetermined logic state when it is determined that the result of the arithmetic subtraction has a negative sign: (d) a one's complement generator circuit responsive to the signal from said first subtracter circuit for generating a signal representative of the one's complement of said result of arithmetic subtraction; (e) a first multiplexer responsive to the signals from said subtractor circuit and said one's complement generator circuit and to the signal from said logic circuit, the first multiplexer having a first state allowing the signal from the one's complement generator circuit to pass therethrough and a second state allowing the signal from the subtractor circuit to pass therethrough, the first multiplexer having said first state in the absence of the signal of said predetermined logic state from said logic circuit and having said second state in the presence of the signal of said predetermined logic state from said logic circuit; (f) a decoder circuit for decoding the signal passed through said first multiplexer for producing a decoded output signal; (g) a single-bit shift circuit for shifting the bits of the decoded output signal by a single bit in a predetermined direction for producing a single-bit shifted output signal, (h) a second multiplexer responsive to the signals from said decoder circuit and said single-bit shift circuit and to the signal from said logic circuit, the second multiplexer having a first state allowing the signal from the decoder circuit to pass therethrough and a second state allowing the signal from the single-bit shift circuit to pass therethrough, the second multiplexer having said first state thereof in the absence of the signal of said predetermined logic state from said logic circuit and said second state thereof in the presence of the signal of said predetermined logic state from said logic circuit; (i) a third multiplexer responsive to the signal indicative of the exponent part of said first number word and the signal indicative of the exponent part of said second number word, and to the signal from said logic circuit, the third multiplexer having a first state allowing the signal indicative of the exponent part of said first number word to pass therethrough and a second state allowing the signal indicative of the exponent part of said second number word to pass therethrough, the third multiplexer having said first state thereof in the absence of the signal of the predetermined logic state from said logic circuit and said second state thereof in the presence of the signal of the predetermined logic state form said logic circuit, the signal indicative of the exponent part of said first number word being passed through the third multiplexer and output as representative of the exponent part of an output number word when the third multiplexer has said first state thereof and the signal indicative of the exponent part of the second number word being passed through the third multiplexer and is output as representative of the exponent part of said output number word when the third multiplexer has said second state thereof; (j) a fourth multiplexer responsive to the signal indicative of the mantissa part of said first number word and the signal indicative of the mantissa part of said second number word, and to the signal from said logic circuit, the fourth multiplexer having a first state allowing the signal indicative of the mantissa part of said first number word to pass therethrough and a second state allowing the signal indicative of the mantissa part of said second number word to pass therethrough, the fourth multiplexer having said first state thereof in the absence of the signal of the predetermined logic state from said logic circuit and said second state thereof in the presence of the signal of the predetermined logic state form said logic circuit; (k) a fifth multiplexer responsive to the signal indicative of the mantissa part of said first number word and the signal indicative of the mantissa part of said second number word, and to the signal from said logic circuit, the fifth multiplexer having a first state allowing the signal indicative of the mantissa part of said second number word to pass therethrough and a second state allowing the signal indicative of the mantissa part of said first number word to pass therethrough, the fifth multiplexer having said first state thereof in the absence of the signal of the predetermined logic state from said logic circuit and said second state thereof in the presence of the signal of the predetermined logic state from said logic circuit; (l) a right circuit responsive to the signals respectively passesd through said second and fifth multiplexers, and operative to make a rightward shift of the digits of the signal from the fourth multiplexer with a bit count represented by the signal from the second multiplexer for producing a signal representative of a right-shifted version of the mantissa part of said second number word; and (m) a dyadic arithmetic circuit having one input terminal responsive to the signal passed through said fourth multiplexer and another input terminal responsive to the signal output from arithmetic addition or subtraction between the input signal representative of the mantissa part of said first number word and the signal representative of the right-shifted version of the original mantissa part of said second number word, the signal resulting from said arithmetic addition or subtraction being output from the arithmetic circuit as being representative of the mantissa part of said output number word.