EP0164451A2
Expired / Lapsed
EP
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An arithmetic processing unit for executing a floating point operation
Assignee: NEC Corp
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Filing: 1984-12-27
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Granted: —
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Expires: 2004-12-27
Abstract
Abstract An arithmetic processing unit executes a first operation to adjust a scale of an exponent part of one data to that of the other data, a second operation to arithmetically calculate the mantissa parts of the two data according to a desired arithmetic operation, and a third operation to correct the exponent part according to the result of the calculation. A proposed arithmetic unit includes an incrementer to increase the exponent part by +1 in parallel with the calculating operation without respect to the overflow and a selector to select the output of the incrementer according to the result of the calculation. Therefore, these three operations can be performed at a high speed in only two cycles.
Inventors
- 👤 Hideo C/O Nec Corp. Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 23:04
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/483; G06F7/485; G06F7/499; G06F7/49905; G06F7/4991; G06F7/49915
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
101 words
An arithmetic processing unit for executing a floating point arithmetic operation comprising a first circuit receiving the respective exponent parts of two floating point data and selecting either one of the two exponent parts according to comparison between said two exponent parts, a second circuit for arithmetically calculating the mantissa parts of said two data, a third circuit, increasing the selected exponent part by +1 in parallel with the arithmetic calculation in said second circuit, and a fourth circuit for selecting either one of said selected exponent part or the incremented exponent part according to the result of said arithmetically calculating.
Claim 2
Dependent Claim
101 words
An arithmetic processing unit for executing a floating point arithmetic operation comprising a first circuit receiving the respective exponent parts of two floating point data and selecting either one of the two exponent parts according to comparison between said two exponent parts, a second circuit for arithmetically calculating the mantissa parts of said two data, a third circuit, increasing the selected exponent part by +1 in parallel with the arithmetic calculation in said second circuit, and a fourth circuit for selecting either one of said selected exponent part or the incremented exponent part according to the result of said arithmetically calculating.
Claim 3
Dependent Claim
42 words
An arithmetic processing unit as claimed in claim 1, in which said fourth circuit selects said incremented exponent part when an overflow occurs in said arithmetic calculating and selects said selected exponent part as it is when the overflow does not occur.
Claim 4
Dependent Claim
24 words
An arithmetic processing unit as claimed in claim 2, in which a carry signal is generated by said second circuit when said overflow occurs.
Claim 5
Dependent Claim
92 words
An arithmetic processing unit comprising a comperator for comparing a scale of an exponent part of one data with that of the other data, a multiplexer for selecting either one of the two exponent parts according to the result of the comparison, an arithmetic circuit for executing an arithmetic operation for two mantissa parts of said data, a correcting circuit for correcting the selected exponent part, and a selector for selecting either the output of said muliplexer or the output of said correcting circuit according to the result of said arithmetic operation.
Claim 6
Dependent Claim
92 words
An arithmetic processing unit comprising a comperator for comparing a scale of an exponent part of one data with that of the other data, a multiplexer for selecting either one of the two exponent parts according to the result of the comparison, an arithmetic circuit for executing an arithmetic operation for two mantissa parts of said data, a correcting circuit for correcting the selected exponent part, and a selector for selecting either the output of said muliplexer or the output of said correcting circuit according to the result of said arithmetic operation.
Claim 7
Dependent Claim
43 words
An arithmetic processing unit as claimed in claim 4, in which said selector selects the output of said multiplexer when a carry signal from said arithmetic circuit is absent and selects the output of said correcting circuit when said carry signal is present.
Claim 8
Dependent Claim
26 words
An arithmetic processing unit as claimed in claim 4, in which said correcting circuit carries out the correcting operation when said arithmetic operation is carried out.
References Cited (Backward Citations)
No citation records indexed.
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