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US4807022A Expired / Lapsed US ⏱️ 0.0 years remaining

Simultaneous formation of via hole and tub structures for GaAs monolithic microwave integrated circuits

Assignee: Raytheon Co
•
Filing: 1987-05-01
•
Granted: 1989-02-21
•
Expires: 2007-05-01
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Abstract

Abstract A method of simultaneously forming recesses for via holes and tub structures in a substrate is provided in a common etching step by defining a mask pattern for the via hole as a single aperture and by defining a mask pattern for the tub structure as a plurality of thin slots. The slots are chosen to have a smaller cross-sectional dimension than the corresponding dimension for the single aperture. Etchant brought into contact with the substrate will etch the substrate at a slower rate in the slots than in the single apertur such that the via hole will etch completely through the substrate whereas, the tub structure will be etched only partially through the substrate. Conductive material is provided in the tub structure and via hole, and a layer of conductive material is disposed thereover, to provide a heat sink/ ground plane conductor. Electrical contact is provided between the frontside of the substrate and the heat sink/ground plane conductor through the via hole, whereas a low thermal impedance path is provided through the tube structure between a heat dissipating element supported on the frontside of the substrate and the heat sink/ground plane conductor.

Inventors

  • 👤 Thomas E. Kazior
  • 👤 Mark S. Durschlag

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 09:24
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/021; H10D; H10D62/00; H10D62/10; H10D62/117; H10P; H10P32/00; H10P32/10; H10P32/16; H10P32/17; H10W20/023; H10W20/0234; H10W20/0242; H10W20/20; H10W20/40; H10W20/41; H10W20/435; H10W40/00; H10W40/10

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 130 words
A semiconductor circuit comprises: a semiconductor substrate supporting a heat dissipating device formed over a first surface thereof; a conductive backplane formed over a second opposite surface of said semiconductor substrate; a conductive contact disposed through said semiconductor substrate provided to make electrical contact between a conductor disposed over the first surface of said semiconductor substrate and the conductive backplane disposed over the second surface of said semiconductor substrate; and a thermally conductive region disposed in a recess provided partially into said semiconductor substrate in a region thereof underlying said heat dissipating element, with said recess having an irregular, nonplanar surface adjacent said heat dissipating element, and said thermally conductive material being disposed in thermal contact with said heat dissipating element and the conductive backplane disposed on the semiconductor substrate.
Claim 2
Dependent Claim 130 words
A semiconductor circuit comprises: a semiconductor substrate supporting a heat dissipating device formed over a first surface thereof; a conductive backplane formed over a second opposite surface of said semiconductor substrate; a conductive contact disposed through said semiconductor substrate provided to make electrical contact between a conductor disposed over the first surface of said semiconductor substrate and the conductive backplane disposed over the second surface of said semiconductor substrate; and a thermally conductive region disposed in a recess provided partially into said semiconductor substrate in a region thereof underlying said heat dissipating element, with said recess having an irregular, nonplanar surface adjacent said heat dissipating element, and said thermally conductive material being disposed in thermal contact with said heat dissipating element and the conductive backplane disposed on the semiconductor substrate.
Claim 3
Dependent Claim 15 words
The circuit of claim 1 wherein the heat dissipating device is a field effect transistor.
Claim 4
Dependent Claim 11 words
The circuit of claim 2 wherein the substrate comprises gallium arsenide.
Claim 5
Dependent Claim 43 words
A semiconductor circuit comprising a semiconductor substrate having a pair of recesses of different depths disposed in a common, first surface of said substrate, with at least one of said recesses disposed partially through said substrate and having an irregular, nonplanar bottom surface.
Claim 6
Dependent Claim 43 words
A semiconductor circuit comprising a semiconductor substrate having a pair of recesses of different depths disposed in a common, first surface of said substrate, with at least one of said recesses disposed partially through said substrate and having an irregular, nonplanar bottom surface.
Claim 7
Dependent Claim 33 words
The semiconductor circuit of claim 4 further comprising a field effect transistor formed over a second surface of said substrate in a region thereof disposed over the recess having the irregular, nonplanar surface.
Claim 8
Dependent Claim 56 words
The semiconductor circuit of claim 4 further comprising: a conductive layer disposed over said first surface of said substrate having the pair of recesses; and a pair of deposits of conductive material each disposed in one of said pair of recesses with said conductive layer disposed in thermal contact with each of said pair of deposits.

References Cited (Backward Citations)

US3509433A Cited
US3823352A Cited
US3986196A Cited
JPS5238885A Cited
US4376287A Cited
US4381341A Cited
US4571611A Cited
US4751562A Cited
JPS59114884A Cited
JPS59123270A Cited
US4601096A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-02-21 1992-08-22 1993-02-21 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-02-21 1996-08-22 1997-02-21 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-02-21 2000-08-22 2001-02-21 $7700.00 Window Closed / Lapsed

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