US4381341A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Two stage etching process for through the substrate contacts
Assignee: Westinghouse Electric Corp
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Filing: 1982-02-01
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Granted: 1983-04-26
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Expires: 2002-02-01
Abstract
Abstract Electrical interconnection paths or vias are provided through relatively thick type III/V semiconductive substrates, such as gallium arsenide, to permit through the substrate electrical interconnection of planar transistor devices. The vias are etched in a two-step process which ensures that the via lateral dimensions are less than the transistor contacts with which they are aligned. The first step comprises selectively thinning the thick substrate from the back surface over an area which encompasses the transistor array formed in the front surface of the substrate. The second step is to etch the individual vias through this prior thinned substrate at areas aligned with the transistor contacts.
Inventors
- 👤 John X. Przybysz
- 👤 Michael C. Driver
- 👤 Harvey C. Nathanson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:08
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/60; H10P50/64; H10P50/642; H10P50/646; H10W; H10W20/00; H10W20/01; H10W20/021; H10W20/023; H10W20/0234; H10W20/0242; H10W20/20; H10W20/211; H10W20/212; H10W20/2125; Y; Y10; Y10S; Y10S438/00; Y10S438/928; Y10S438/977
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
134 words
Method of providing a plurality of electrical interconnection vias through an integrated circuit substrate wherein a plurality of transistor devices are formed on one side of the substrate with a plurality of transistor contacts disposed on the substrate surface in electrical contact with transistor regions, wherein the respective interconnection vias are aligned with and are smaller in area than the transistor contacts with which they are respectively aligned, which method comprises; (a) selectively thinning the substrate from the side opposed to the side on which the transistor devices and transistor contacts are disposed, which selectively thinned substrate area exceeds the transistor contact area; (b) etching through portions of the selectively thinned substrate area which is aligned with the transistor contacts to produce electrical interconnection vias of an area smaller than the transistor contact area.
Claim 2
Dependent Claim
134 words
Method of providing a plurality of electrical interconnection vias through an integrated circuit substrate wherein a plurality of transistor devices are formed on one side of the substrate with a plurality of transistor contacts disposed on the substrate surface in electrical contact with transistor regions, wherein the respective interconnection vias are aligned with and are smaller in area than the transistor contacts with which they are respectively aligned, which method comprises; (a) selectively thinning the substrate from the side opposed to the side on which the transistor devices and transistor contacts are disposed, which selectively thinned substrate area exceeds the transistor contact area; (b) etching through portions of the selectively thinned substrate area which is aligned with the transistor contacts to produce electrical interconnection vias of an area smaller than the transistor contact area.
Claim 3
Dependent Claim
79 words
The method set forth in claim 1, wherein the selective thinning of the substrate is carried out by mounting the substrate transistor device side down on a glass support slide, depositing a first photoresist layer on the exposed back surface of the substrate, and selectively exposing the photoresist to polymerizing radiation, and etching away these selectively exposed photoresist layer areas, and thereafter etching away the substrate portions from which the photoresist has been etched to selectively thin the substrate.
Claim 4
Dependent Claim
82 words
The method set forth in claim 2, wherein the etchings through portions of the selectively thinned substrate to produce the interconnection vias is carried out by depositing a second photoresist layer on the selectively thinned substrate, selectively exposing the second photoresist layer to polymerizing radiation in substrate areas aligned with but smaller in area then the transistor contacts, and etching away these selectively exposed photoresist areas to permit etching through portions of the selectively thinned substrate to produce the electrical interconnection vias.
Claim 5
Dependent Claim
53 words
The method set forth in claim 3, wherein conductive metal is deposited in the electrical interconnection vias making electrical contact with the transistor contacts with which the vias are aligned, and which deposited conductive metal extends through the substrate to a ground plane electrode deposited on the substrate surface opposite the transistor surface.
References Cited (Backward Citations)
US3493820A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-04-25 | 1986-10-25 | 1987-04-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-04-25 | 1990-10-25 | 1991-04-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-04-25 | 1994-10-25 | 1995-04-26 | $7700.00 | Window Closed / Lapsed |