Patent US4803705A successfully refreshed from Google Patents.
US4803705A
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Analog phase locked loop
Assignee: Microsemi Semiconductor ULC
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Filing: 1987-08-19
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Granted: 1989-02-07
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Expires: 2007-08-19
Abstract
Abstract A phase locked loop for synchronizing a local digital signal with an incoming data signal is described. Parallel phase and frequency detectors compare the local and incoming signals and generate control pulse signals for controlling the frequency of a voltage controlled oscillator which generates the local digital signal. Logic circuitry is included in both the phase and frequency detectors for adjusting the generated control pulse signals in the event of detection of elongated pulse widths of the incoming data signal, indicating one of either an absence of incoming data signal or a bipolar violation in the event the data signals are ASI encoded. The phase locked loop is characterized by quick pull-in time, large pull-in frequency range, accurate clocking and low cost.
Inventors
- 👤 Peter Gillingham
- 👤 Jan H. Erkku
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:44
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0054; H04L7/0066; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/089; H03L7/0891; H03L7/10; H03L7/113; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
201 words
A phase locked loop for synchronizing a local digital signal with a remote digital signal, comprised of: (a) first means for receiving and comparing said local and remote digital signals, and upwardly adjusting the frequency of said local signal in the event the local signal frequency is less than the remote signal frequency, and downwardly adjusting the frequency of said local signal in the event the local signal frequency is greater than the remote signal frequency, (b) second means for receiving and comparing said local and remote signals, and upwardly adjusting the frequency of said local signal in the event the local signal phase lags the remote signal phase, and downwardly adjusting the frequency of said local signal in the event the local signal phase leads the remote signal phase, and (c) means for detecting elongated pulse widths of said remote digital signal and upwardly adjusting the frequency of said local signal in response thereto, for counteracting downward adjustment of the local signal frequency by said first and second means in response to detection of said elongated remote signal pulse widths, whereby said local and remote signals are phase and frequency locked regardless of pulse width anomalies of said remote signal.
Claim 2
Dependent Claim
201 words
A phase locked loop for synchronizing a local digital signal with a remote digital signal, comprised of: (a) first means for receiving and comparing said local and remote digital signals, and upwardly adjusting the frequency of said local signal in the event the local signal frequency is less than the remote signal frequency, and downwardly adjusting the frequency of said local signal in the event the local signal frequency is greater than the remote signal frequency, (b) second means for receiving and comparing said local and remote signals, and upwardly adjusting the frequency of said local signal in the event the local signal phase lags the remote signal phase, and downwardly adjusting the frequency of said local signal in the event the local signal phase leads the remote signal phase, and (c) means for detecting elongated pulse widths of said remote digital signal and upwardly adjusting the frequency of said local signal in response thereto, for counteracting downward adjustment of the local signal frequency by said first and second means in response to detection of said elongated remote signal pulse widths, whereby said local and remote signals are phase and frequency locked regardless of pulse width anomalies of said remote signal.
Claim 3
Dependent Claim
30 words
A phase locked loop as defined in claim 1, further including a voltage controlled oscillator for generating a high frequency oscillator output signal from which said local digital signal is
Claim 4
Dependent Claim
51 words
A phase locked loop as defined in claim 2, wherein said first and second means are comprised of a frequency detector and phase detector respectively, for generating up and down control voltage signals for application to said voltage controlled oscillator in order to adjust the frequency of said local digital signal.
Claim 5
Dependent Claim
55 words
A phase locked loop as defined in claim 3, wherein said means for detecting elongated pulse widths is comprised of logic circuitry for generating an up control voltage signal in the event one or both of said phase and frequency detectors generate down control voltage signals for more than one cycle of said local signal.
Claim 6
Dependent Claim
43 words
A phase locked loop as defined in claim 4, further including a loop filter for summing and integrating said control voltage signals and generating a DC control signal for application to a control voltage input of said voltage controlled oscillator in response thereto.
Claim 7
Dependent Claim
41 words
A phase locked loop as defined in claim 4, wherein said voltage controlled oscillator is further comprised of a digital signal divider for receiving and frequency dividing said high frequency oscillator output signal and generating said local signal in response thereto.
Claim 8
Dependent Claim
43 words
A phase locked loop as defined in claim 3, further including a loop filter for summing and integrating said control voltage signals and generating a DC control signal for application to a control voltage input of said voltage controlled oscillator in response thereto.
Claim 9
Dependent Claim
46 words
A phase locked loop as defined in claim 7, wherein said loop filter is comprised of an operational amplifier, and a resistor and capacitor connected in series to an inverting input of said amplifier and an output thereof, a non-inverting input thereof being connected to ground.
Claim 10
Dependent Claim
32 words
A phase locked loop as defined in claim 8, wherein said up and down control voltage signals are applied to the inverting input of said operational amplifier via respective current source circuits.
Claim 11
Dependent Claim
25 words
A phase locked loop as defined in claim 9, wherein said current source circuits generate current signals having magnitudes characterized by a predetermined current reference.
Claim 12
Dependent Claim
72 words
A phase locked loop as defined in claim 3, wherein said means for detecting is comprised of logic circuitry for upwardly adjusting one or both of said up and down control voltage signals in the event a corresponding one or both of said control voltage signals were previously downwardly adjusted for more than one cycle of said local digital signal, as a result of a bipolar violation followed by a zero bit.
Claim 13
Dependent Claim
41 words
A phase locked loop as defined in claim 2, wherein said voltage controlled oscillator is further comprised of a digital signal divider for receiving and frequency dividing said high frequency oscillator output signal and generating said local signal in response thereto.
Claim 14
Dependent Claim
45 words
A phase locked loop as defined in claim 12, wherein said high frequency signal has a frequency of approximately 4.096 megahertz, and said divider divides the 4.096 megahertz high frequency signal by 21.33 and generates said local oscillator signal at 192 kHz in response thereto.
Claim 15
Dependent Claim
41 words
A phase locked loop as defined in claim 3, wherein said voltage controlled oscillator is further comprised of a digital signal divider for receiving and frequency dividing said high frequency oscillator output signal and generating said local signal in response thereto.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-07 | 1992-08-08 | 1993-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-07 | 1996-08-08 | 1997-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-07 | 2000-08-08 | 2001-02-07 | $7700.00 | Window Closed / Lapsed |